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HYNIX SEMICONDUCTOR INC. 8-BIT SINGLE-CHIP MICROCONTROLLERS
GMS81C5108
User's Manual (Ver. 1.0)
Version 1.0 Published by MCU Application Team (c)2001 Hynix Semiconductor Inc. All rights reserved. 200
Additional information of this manual may be served by Hynix Semiconductor offices in Korea or Distributors and Representatives listed at address directory. Hynix Semiconductor reserves the right to make changes to any information here in at any time without notice. The information, diagrams and other data in this manual are correct and reliable; however, Hynix Semiconductor is in no way responsible for any violations of patents or other rights of the third party generated by the use of this manual.
GMS81C5108
Table of Contents
1. OVERVIEW ...........................................1
Description .........................................................1 Features .............................................................1 Development Tools ............................................2 Ordering Information 8-Bit Capture Mode ......................................... 50 16-bit Capture Mode ....................................... 53 8-Bit (16-Bit) Compare OutPut Mode .............. 53 PWM Mode ..................................................... 53
13. Watch Timer/Watch Dog Timer......... 56
Watch Timer .................................................... 56 Watch Dog Timer ............................................ 57
2. BLOCK DIAGRAM ................................3 3. PIN ASSIGNMENT ...............................4 4. PACKAGE DIAGRAM ...........................5 5. PIN FUNCTION .....................................6 6. PORT STRUCTURES ...........................8 7. ELECTRICAL CHARACTERISTICS ...11
Absolute Maximum Ratings .............................11 Recommended Operating Conditions ..............11 DC Electrical Characteristics ...........................12 LCD Characteristics .........................................13 A/D Converter Characteristics .........................13 AC Characteristics ...........................................14 Serial I/O Characteristics .................................15 Typical Characteristics..................................... 16
14. Analog To Digital Converter ..............58 15. Buzzer Output Function ....................60 16. Serial Communication Interface ........62
Data Transmit/Receive Timing........................ 63 The method of Serial I/O ................................. 64
17. INTERRUPTS ...................................65
Interrupt Sequence .......................................... 66 BRK Interrupt .................................................. 68 Multi Interrupt .................................................. 68 External Interrupt ............................................. 69
18. KEY SCAN ........................................70 19. LCD DRIVER .................................... 71
Configuration of LCD driver ............................. 71 Control of LCD Driver Circuit ........................... 72 LCD Display Memory ...................................... 73 Control Method of LCD Driver ......................... 74
8. MEMORY ORGANIZATION ................18
Registers ..........................................................18 Program Memory .............................................21 Data Memory ................................................... 24 Addressing Mode ............................................. 27
20. Remocon Carrier Generator ............. 76
Remocon Signal Output Control ..................... 76 Carrier Frequency ........................................... 77
9. I/O PORTS ..........................................31
Registers for Port .............................................31 I/O Ports Configuration ....................................32
21. OSCILLATOR CIRCUIT ....................80 22. RESET ..............................................81
External Reset Input ........................................ 81 Watchdog Timer Reset ................................... 81
10. CLOCK GENERATOR ......................34
Operation Mode ...............................................36 Operation Mode Switching ...............................37 POWER SAVING OPERATION .......................39
11. BASIC INTERVAL TIMER .................43 12. Timer / Counter .................................45
8-Bit Timer/Counter Mode ................................48 16 Bit Timer/Counter Mode ..............................50
23. SUPPLY VOLTAGE DETECTION ....82 24. DEVEMOPMENT TOOLS .................83
OTP Programming .......................................... 83 Emulator S/W Setting ...................................... 84
A. CONTROL REGISTER LIST ................. i B. INSTRUCTION .................................... iii
Terminology List................................................ iii
Instruction Map ..................................................iv Instruction Set ....................................................v
C. MASK ORDER SHEET ....................... xi
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GMS81C5108
GMS81C5108
CMOS SINGLE-CHIP 8-BIT MICROCONTROLLER WITH LCD CONTROLLER/DRIVER AND INFRARED REMOTE CONTROL TRANSMITTERS
1. OVERVIEW
1.1 Description
The GMS81C5108 is an advanced CMOS 8-bit microcontroller with 8K bytes of ROM. The device is one of GMS800 family. The Hynix GMS81C5108 is a powerful microcontroller which provides a high flexibility and cost effective solution to many LCD applications. The GMS81C5108 provides the following standard features: 8K bytes of ROM, 192 bytes of RAM, 37 Nibbles of Display RAM, 8/16-bit timer/counter, on-chip oscillator and clock circuitry. In addition, the GMS81C5108 supports power saving modes to reduce power consumption. This document is only explained for the base of GMS81C5108, the eliminated functions are same as below.
Device name GMS81C5108 GMS87C5108 ROM Size 8K bytes OTP Size 8K bytes RAM Size 192 bytes 192bytes I/O 24 24 Package 80QFP 80QFP
1.2 Features
* 8K Bytes of On-chip Program Memory * 192 Bytes of On-chip Data RAM * 37 Nibbles of Display RAM * Instruction Cycle Time: - 1us at 4MHz (2 cycle NOP instruction) * 24 Programmable I/O pins * 2V to 4V Operating Range * Dual Clock Operation - main : 400kHz ~ 4.2MHz - sub. : 32.768kHz * One 8-bit Basic Interval Timer/Counter * Key Scan Interrupt * Two 8-bit Timer/ Counter (It can be used one 16-bit Timer/Counter) * Watch Timer (2Hz, 4Hz, 16Hz, 1/64Hz) * 8-bit Serial I/O (SIO) * One 10-bit High Speed PWM Output * Supply Voltage Detector(SVD) - 2 level detector (2.2V, 1.7V) * Carrier Generator for Remote Controller * 11 Interrupt sources - 3 External interrupts (INT0 ~ 2) - 8 Internal interrupts (BIT, Timer x 2, WT, A/DC, SIO, REM, Keyscan) * 6-bit Buzzer Driving port - 500Hz ~ 250kHz (@4MHz) * 4-channel 8-bit On-chip A/D Converter * Power Saving Mode - STOP, SLEEP, Sub Active mode * LCD display/controller (LCDC) - Static Mode (37Seg x 1Com, 1/3 Bias) - 1/2 Duty Mode (36Seg x 2Com, 1/3 Bias) - 1/3 Duty Mode (35Seg x 3Com, 1/3 Bias) - 1/4 Duty Mode (34Seg x 4Com, 1/3 Bias) * LCD Display Voltage Booster
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1.3 Development Tools
98TM.
Note: There are several setting switches in the Emulator. User should read carefully and do setting properly before developing the program refer to "24.2 Emulator S/W Setting" on page 84. Otherwise, the Emulator may not work properly.
Please contact sales part of Hynix Semiconductor.
Software Hardware (Emulator) OTP Writer
- MS- Window base assembler - Linker / Editor / Debugger - CHOICE-Dr. - CHOICE-Dr. EVA 81C51 B/D - CHOICE - SIGMA (Single writer) - CHOICE - GANG4 (Gang writer)
The GMS81C5108 is supported by a full-featured macro assembler, an in-circuit emulator CHOICE-Dr.TM and OTP programmers. There are two different type programmers such as single type and gang type. For mode detail, refer to OTP Programming chapter. Macro assembler operates under the MS-Windows 95/
1.4 Ordering Information
Device name Mask ROM version OTP ROM version GMS81C5108 GMS87C5108 ROM Size (bytes) 8K bytes 8K bytes OTP RAM size 192 bytes 192 bytes Package 80QFP 80QFP
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2. BLOCK DIAGRAM
Common Drive Output COM0 COM1/SEG36 COM2/SEG35 COM3/SEG34
Segment Drive Output SEG0 ~ SEG33
VCL0 VCL1 VCL2 CAPH CAPL VLCDC
LCD Display Voltage Booster LCD Controller/Driver (LCDC)
PSW
ALU
Accumulator
Stack Pointer
Data Memory LCD Display Memory
PC
Interrupt Controller RESET System controller System Clock Controller Timing generator XIN XOUT SXIN SXOUT High freq. Low freq. Clock Generator Watch/Watch Dog Timer 8-bit A /D C onverter 8-bit B asic Interval Tim er
Program Memory Data Table
PC 8/16-bit SIO Tim er/C ounter
High Speed PWM
VDD VSS AVDD AVSS Power Supply
Power Supply Circuit
R3
R2
R1
R0
Buzzer Driver
Remocon (REM)
VREG
WDTOUT
R30 R31 / PWM R32 R33
R20 / AN0 R21 / AN1 R22 / AN2 R23 / AN3
R10 / KS0 R11 / KS1 R12 / KS2 R13 / KS3 R14 / KS4 R15 / KS5 R16 / KS6 R17 / KS7
R00 / INT0 R01 / INT1 R02 / INT2 R03 / EC0 R04 / BUZ R05 / SCK R06 / SO R07 / SI
REMOUT
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4
RESET VREG SEG34 / COM3 CAPH WDTOUT VLCDC SXOUT CAPL SXIN COM0 VCL2 VCL1 VCL0 79 XOUT XIN VDD REMOUT R07 / SI R06 / S0 R05 / SCK R04 / BUZ R03 / EC0 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 R02 / INT2 R01 / INT1 R33 R32 R31 / PWM R30 R17 / KS7 R16 / KS6 R15 / KS5 R14 / KS4 R13 / KS3 R12 / KS2 R11 / KS1 R10 / KS0 R00 / INT0 78 77 76 75 74 73 72 71 70 69 68 67 66 65 SEG35 / COM2 SEG36 / COM1 SEG33 80 SEG32 1 64 63 62 61 60 59 58 57 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9
GMS81C5108
3. PIN ASSIGNMENT
GMS81C5108
VSS AVSS AVDD
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
SEG0
R20 / AN0
R21 / AN1
R22 / AN2
R23 / AN3
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GMS81C5108
4. PACKAGE DIAGRAM
24.15 23.65 20.10 19.90
UNIT: mm
max ----------min
18.15 17.65
14.10 13.90
SEE DETAIL "A"
0-7
3.10 max. 0.8 BSC
1.03 0.73 1.95 REF
0.45 0.30
0.36 0.10
DETAIL "A"
Figure 4-1 Package Diagram
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GMS81C5108
5. PIN FUNCTION
VDD: Supply voltage. VSS: Circuit ground. AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. AVSS: ADC circuit ground RESET: Reset the MCU. WDTOUT: Output for detection of a program malfunction. If the user wants to use this pin, connect it to the RESET pin. REMOUT: Signal output of an infrared remote controller. XIN: Input to the inverting oscillator amplifier and input to the internal main clock operating circuit. XOUT: Output from the inverting oscillator amplifier. SXIN: Input to the internal sub system clock operating circuit. SXOUT: Output from the inverting subsystem oscillator amplifier. SEG0~SEG36: Segment signal output pins for the LCD display. See "19. LCD DRIVER" on page 71 for details. COM0~COM3: Common signal output pins for the LCD display. See "19. LCD DRIVER" on page 71 for details. SEG34~SEG36 and COM1~COM3 are selected by LCDD of the LCR register. R00~R07: R0 is an 8-bit CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. Also, pull-up resistors and opendrain outputs can be assigned by software.
used as outputs or inputs or schmitt trigger inputs. Also, pullup resistors and open-drain outputs can be assigned by software.
In addition, R1 serves the functions of the various following special features.
Port pin R10 R11 R12 R13 R14 R15 R16 R17 Alternate function KS0 (Key scan input 0) KS1 (Key scan input 1) KS2 (Key scan input 2) KS3 (Key scan input 3) KS4 (Key scan input 4) KS5 (Key scan input 5) KS6 (Key scan input 6) KS7 (Key scan input 7)
R20~R23: R2 is a 4-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. Also, pull-up resistors and opendrain outputs can be assigned by software.
In addition, R2 serves the functions of the various following special features.
Port pin R20 R21 R22 R23 Alternate function AN0 (Analog Input Port0) AN1 (Analog Input Port1) AN2 (Analog Input Port2) AN3 (Analog Input Port3)
R30~R33: R3 is a 4-bit CMOS bidirectional I/O port. Each pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. Also, pull-up resistors and opendrain outputs can be assigned by software.
In addition, R0 serves the functions of the various following special features.
Port pin R00 R01 R02 R03 R04 R05 R06 R07 Alternate function INT0 (External interrupt 0) INT1 (External interrupt 1) INT2 (External interrupt 2) Event counter input Buzzer Output SCK (SPI CLK Input/Output) SO (SPI Serial Data Output) SI (SPI Serial Data Input)
In addition, R3 serves the functions of the various following special features.
Port pin R31 Alternate function PWM (PWM Output)
VCL0~VCL2: Power supply pins for the LCD driver. The voltage on each pin is VCL2> VCL1> VCL0. See "19. LCD DRIVER" on page 71 for details. VLCDC: LCD drive voltage booster reference. CAPH, CAPL: LCD drive voltage booster capacitor. VREG: Output of the voltage regular for the sub clock oscillation circuit. Connect external 0.1uF capacitor to this pin when using the sub system clock.
R10~R17: R1 is an 8-bit CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be
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Primary Function PIN NAME VDD VSS AVDD AVSS RESET WDTOUT REMOUT XIN, XOUT SXIN, SXOUT VREG VCL0~VCL2 VLCDC CAPH,CAPL Pin No. I/O 62 33 35 40 65 67 61 63, 64 68, 69 66 70,72,73 71 74,75 I O O I,O I,O O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O General I/O port Description Supply Voltage Circuit Ground Supply Voltage for ADC Ground for ADC Reset (low active) Watch dog output Remocon output Main clock oscillator Sub clock oscillator Sub clock voltage LCD drive voltage LCD drive voltage booster reference LCD drive voltage booster capacitor LCD segment output LCD common output LCD common output.
Secondary Function State @ Reset I/O I I I I O I/O O I I I O Description LCD segment output Interrupt Input Interrupt Input Interrupt Input Event counter input Buzzer output Serial clock I/O Serial Data Output Serial Data Input Key wake-up input A/D converter analog input PWM output Input port State of before STOP Internal VCL0 Connected Internal VCL0 Connected `L' input Floating (To be connect Pull-up) `H' input State of before STOP State @ STOP
`L' output Oscillation Oscillation State of before STOP State of before STOP `L', `L'
SEG0 ~ SEG33 34, 32~1 COM0 SEG34/COM3 SEG35/COM2 SEG36/COM1 R00/INT0 R01/INT1 R02/INT2 R03/EC0 R04/BUZ R05/SCK R06/SO R07/SI R10 ~ R17/ KS0 ~ KS7 R20 ~ R23/ AN0 ~ AN3 R30,R32,R33 R31/PWM 76 79~77 41 54 55 56 57 58 59 60 42~49 36~39 50,52,53 51
Segment output Common output Common output
Table 5-1 Port Function Description
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GMS81C5108
6. PORT STRUCTURES
R00~R03/INT0~INT2, R03/EC0, R07/SI
P u ll up R e g.
R10~R17/KS0~KS7
Pull-up Tr.
P ull up R eg .
Pull-up Tr.
Open Drain Reg. Data Bus Data Reg.
VDD Data Bus
Open Drain Reg. Data Reg.
VDD
Dir. Reg. PMR<0:3,7> MUX RD INT0 ~ IN T2 EC0,SI Noise Canceller RD VSS
Pin
Dir. Reg. KSMR<0:7> MUX RD RD Key Scan KS0 ~ KS7 Noise Canceller Key Scan Enable VSS
Pin
R04/BUZ, R06/SO
Pull up Reg. VDD Open Drain Reg. Data Bus Data Reg. BUZ,SO Dir. Reg. Pin MUX RD RD MUX VSS Data Bus
P u ll up R e g.
Pull-up Tr.
R20~R23/AN0~AN3
Pull-up Tr.
Open Drain Reg. Data Reg.
VDD
Dir. Reg. VSS RD RD
Pin
R05/SCK
Pull up Reg. VDD Open Drain Reg. Data Bus Data Reg. SCK(OUT) Dir. Reg. SCK(IN)_EN MUX RD SCK(IN) Noise Canceller RD Pin VSS Pull-up Tr. A/D converter AN0 ~ AN3
A/D Enable channel select
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R30, R32, R33
COM0
VCL2 or VCL1 VCL2 Frame Counter
P u ll up R e g.
Pull-up Tr.
Open Drain Reg. Data Bus Data Reg.
VDD LCD Control VCL1 or VSS Pin
Dir. Reg. VSS
Pin
MUX RD
COM1/SEG36, COM2/SEG35, COM3/SEG34
VCL2 or VCL1 VCL2 DB LCD Data Reg.
RD
R31
Pull up Reg. VDD Open Drain Reg. Data Bus Data Reg. PWMO Dir. Reg. Pin MUX RD RD VSS
Frame Counter Pull-up Tr. LCD Control VCL1 or VSS Pin
VCL0 ~ VCL2, CAPH, CAPL
VCL0 ~ VCL2, CAPH, CAPL Pin
SEG0 ~ SEG33
VCL2 or VCL1 VCL2 DB LCD Data Reg.
VLCDC, VREG
VDD VCLDC, VREG Pin
Frame Counter LCD Control VCL1 or VSS Pin
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GMS81C5108
REMOUT
VDD VDD
XIN, XOUT (Crystal or Ceramic resonator Option)
VDD Main frequency clock XOUT Pin VDD VSS VDD
REMOUT
XIN
RESET
STOP VSS
GMS87C5108 (OTP)
XIN, XOUT (RC Option)
Internal RESET RESET Noise Canceller VDD Main frequency clock XOUT VDD Mask Option Default no pull-up Internal Cap. = 5.0pF VDD RESET Noise Canceller STOP VSS RC Oscillator XIN VSS VDD
VSS
GMS81C5108 (MASK)
VDD
Internal RESET
SXIN, SXOUT
VSS VDD
WDTOUT
Sub clock VDD VSS VDD SXOUT
WDTOUT WDTOUTEN
Pin
VSS SXIN
VSS
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7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
Supply voltage ........................................... -0.3 to +7.0 V Storage Temperature ................................-40 to +125 C Voltage on any pin with respect to Ground (VSS) ............................................................... -0.3 to VDD+0.3 Maximum current sunk by (IOL per I/O Pin) ........20 mA Maximum output current sourced by (IOH per I/O Pin) ...............................................................................15 mA Maximum current (IOL) ....................................100 mA Maximum current (IOH)...................................... 60 mA
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
7.2 Recommended Operating Conditions
Specifications Parameter Symbol Condition Min. Supply Voltage Main Operating Frequency Sub Operating Frequency Operating Temperature VDD fMAIN fSUB TOPR fMAIN=4MHz fSUB=32.768kHz VDD=2~4V VDD=2~4V 2.0 0.4 -20 Typ. 32.768 Max. 4.0 4.2 70 V MHz kHz C Unit
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GMS81C5108
7.3 DC Electrical Characteristics
(TA=-20~70C, VDD=AVDD=2~4V, VSS=AVSS=0V)
Parameter Symbol VIH1 Input High Voltage VIH2 VIH3 VIL1 Input Low Voltage VIL2 VIL3 VOH1 Output High Voltage VOH2 VOH3 VOL1 Output Low Voltage VOL2 VOL3 Input High Leakage Current Input Low Leakage Current Output High Leakage Current Output Low Leakage Current Pull-up Resister IIH IIL IOH IOL RP1 RP2 RF1 RF2 FRC VREG IDD1 IDD2 Supply Current IDD3 IDD4 IDD5 R0~R3 RESET, XIN, INT0~INT2, EC0, SI, SCK SXIN R0~R3 RESET, XIN, INT0~INT2, EC0, SI, SCK SXIN R0~R3, IOH1=-0.7mA XOUT, IOH2=-50A SXOUT, IOH3=-5A R0~R3, WDTOUT, IOL1=1mA XOUT, IOL2=50A SXOUT, IOL3=5A R0~R3, VIN=VDD R0~R3, VIN=0V REMOUT, VDD=3V, VOH= VDD-1.0V REMOUT, VDD=3V, VOL= 1.0V R0~R3, VDD=3V RESET, VDD=3V (GMS81C5108 Mask Option) Main OSC Feedback Resister VDD=3V Sub OSC Feedback Resister VDD=3V R=30k, VDD=3V VREG=0.2uF Main Active Mode VDD=4V10%, XIN=4MHz, SXIN=0 Main Sleep Mode VDD=4V10%, XIN=4MHz, SXIN=0 Stop Mode V D D =4V 10% , XIN=0, SXIN=0 Sub Active mode1 VDD=3V10%, XIN=0, SXIN=32.768kH z Sub Sleep mode VDD=4V10%, XIN=0, SXIN=32.768kH z Condition Specifications Min. 0.7VDD 0.8VDD 0.8VREG 0 0 0 VDD-0.3 VDD-0.5 VREG-0.3
-
Typ. 100 60 2 2.2 2.7 0.47 2.0 35(70) 6.0
Max. VDD VDD VREG 0.3 VDD 0.2VDD 0.2VREG 0.4 0.5 0.5 1
Unit
V
V
V
V
-30 0.5 50 30 0.5 5. 1 2.0 -
A -1 -5 mA 3 200 120 1.5 15 3 2.4 4.0 mA 1.2 10 80(150) 15 A k
Feed Back Resister RC Oscillator Frequency VREG Voltage
M MHz V
1. IDD4 is tested by only nop operation. The value of ( ) is tested at OTP.
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7.4 LCD Characteristics
(TA=-20~70C, VDD=AVDD=2~4V, VSS=AVSS=0V)
Specifications Parameter Symbol Condition Min. VLCDC Output Voltage LCD Reference Output Voltage Double Output Voltage Triple Output Voltage LCD Common Output Current LCD Segment Output Current VLCDC VCL0 VCL1 VCL2 ICOM ISEG VDD=3V, TA=25C, R1=1M, R2=300k External Variable Resistance (0 to 1M) C1~C4=0.47uF C1~C4=0.47uF Output Voltage Deviation=0.2V Output Voltage Deviation=0.2V 0.7 0.9 1.9VCL0 2.85VCL0 30 5 Typ. 0.9 2.0VCL0 3.0VCL0 Max. 1.1 V 2.0 A - V Unit
7.5 A/D Converter Characteristics
(TA=25C, VDD=3V, AVDD=3.072V, VSS=AVSS=0V)
Specifications Parameter Analog Power Supply Input Voltage Range Analog Input Voltage Range Current Following Between AVDD and AVSS Overall Accuracy Non Linearity Error Differential Non Linearity Error Zero Offset Error Full Scale Error Gain Error Conversion Time Symbol AVDD VAN IAVDD CAIN NNLE NDNLE NZOE NFSE NGE TCONV Condition Min. fMAIN=4MHz AVSS AVSS-0.3 Typ. 1.0 1.0 1.0 0.5 0.25 1.0 Max. AVDD AVDD+0.3 200 2.0 2.0 2.0 1.5 0.5 1.5 30 S LSB V A Unit
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GMS81C5108
7.6 AC Characteristics
(TA=25C, VDD=4V, AVDD=4V, VSS=AVSS=0V)
Specifications Parameter Main Operating Frequency Sub Operating Frequency System Clock Frequency1 Main Oscillation Stabilization Time (4MHz) Main Oscillation Stabilization Time (910kHz) Main Oscillation Stabilization Time (455kHz) Sub Oscillation Stabilization Time External Clock "H" or "L" Pulse Width Interrupt Pulse Width RESET Input Pulse "L" Width Event Counter Input "H" or "L" Pulse Width
1.SCMR=XXXX000X that is fMAIN/2
Symbol fMCP fSCP tSYS
Pins Min. XIN SXIN 0.455 30 0.477 Typ. 32.768 1 Max. 4.19 35 4.395 20 60 100 2 -
Unit MHz kHz S
tMST
XIN, XOUT
-
mS
tSST tMCPW tSCPW tIW tRST tECW
SXIN, SXOUT XIN SXIN INT0, INT1, INT2 RESET EC0
80 5 2 8 2
S nS S tSYS tSYS tSYS
1/fMCP
tMCPW
tMCPW 0.8VDD
XIN
0.2VDD
tSYS 1/fSCP tSCPW tSCPW 0.8VDD
SXIN
0.2VDD
tRST
RESET
0.2VDD tECW tECW 0.8VDD 0.2VDD
EC0
Figure 7-1 AC Timing Chart
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7.7 Serial I/O Characteristics
(TA=25C, VDD=AVDD=2~4V, VSS=AVSS=0V)
Specifications Parameter SCK Input Clock Pulse Period SCK Input Clock "H" or "L" Pulse Width SCK Output Clock Cycle Time SCK output Clock "H" or "L" Pulse Width SCK output Clock Delay Time SI input Setup Time (External SCK) SI input Setup Time (Internal SCK) SI input Hold Time Symbol tSCYC tSCKW tSCYC tSCKW tDS tESUS tISUS tHS SI SCK Pins Min. 2tSYS+200 tSYS+70 4tSYS 2tSYS-30 100 100 tSYS+100 Typ. Max. 16tSYS nS 100 Unit
tSCYC tSCKW tSCKW 0.8VDD
SCK
0.2VDD
tSUS
tHS 0.8VDD 0.2VDD
SI
tDS
SO
0.8VDD 0.2VDD
Figure 7-2 Serial I/O Timing Chart
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7.8 Typical Characteristics
These graphs and tables are for design guidance only and are not tested or guaranteed.
In some graphs or tables, the datas presented are outside specified operating range (e.g. outside specified VDD range). This is for information only and devices are guaranteed to operate properly only within the specified range.
The data is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation
IOH-VOH, VDD=4.2V
IOH (mA) -16 -14 -12 -10 -8 -6 -4 -2 0
1.0 2.0 3.0
-20C 25C 70C
IOL (mA) 40
IOL-VOL, VDD=4.2V
-20C 25C 70C R (k) 200
R-Ta - R0,R1,R2,R3 pin
30
20
100
VDD=4.0V
10 0 VOH 4.0 (V) 1.0 2.0 3.0 4.0 VOL (V) -25 0 25 50 75 Ta (C)
VDD-VIH1
VIH1 (V) 4 3 2 1 0 2 2.5 3 3.5 VDD 4 (V)
VDD-VIH2
VIH2 (V) 4 3 2 1 0 2 2.5 3 3.5 VDD 4 (V) 0 50
R0~R3 pin
fMAIN=4MHz Ta=25C
RESET,XIN,INT0~INT2,EC0.SI.SCK
fMAIN=4MHz Ta=25C
R-Ta -
R (k) 100
RESET pin
VDD=4.0V
-25
0
25
50
75
Ta (C)
VDD-VIL1
VIL1 (V)
VDD-VIL2
VIL1 (V)
R0~R3 pin
fMAIN=4MHz Ta=25C
RESET,XIN,INT0~INT2,EC0.SI.SCK
fMAIN=4MHz Ta=25C
2
2
1
1
0 2 2.5 3 3.5
VDD 4 (V)
0 2 2.5 3 3.5
VDD 4 (V)
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GMS81C5108
fMAIN-VDD
fMAIN (MHz) 4 R = 20k 3 4 2 R = 47k R = 68k 1 R = 100k 1 VDD 2 2.5 3 3.5 4 (V) 0 3 2 Ta=25C
Operating Area
fMAIN (MHz) Ta= -20~70C (Main-clock) 6 5
0
2
2.5
3
3.5
4
VDD 4.5 (V)
IDD (mA) 4 3 2 1 0
Normal Mode (Main opr.) IDD1-VDD
Ta=25C fMAIN=4MHz
IDD (A) 400 300 200 100
Sleep Mode (Main opr.) ISLEEP (IDD2)-VDD
Ta=25C fMAIN=4MHz IDD (A) 4 3 2 1 VDD 4 (V) 0
Stop Mode ISTOP (IDD3)-VDD
Ta=25C fMAIN=0Hz
2
2.5
3
3.5
VDD 4 (V)
0 2 2.5 3 3.5
2
2.5
3
3.5
VDD 4 (V)
IDD (A) 100 75 50 25 0
Normal Mode (Sub opr.) IDD4-VDD
fSXIN=32kHz Ta=25C IDD (A) 8 6 4 2 VDD 4 (V) 0
Sleep Mode (Sub opr.) ISLEEP (IDD5)-VDD
f SX IN = 3 2 kH z Ta=25C
2
2.5
3
3.5
2
2.5
3
3.5
VDD 4 (V)
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8. MEMORY ORGANIZATION
The GMS81C5108 has separate address spaces for Program memory, Data Memory and Display memory. Program memory can only be read, not written to. It can be up to 8K bytes of Program memory. Data memory can be read and written to up to 192 bytes including the stack area. Display memory has prepared 37 bytes for LCD.
8.1 Registers
This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register.
A X Y SP PCH PCL PSW ACCUMULATOR X REGISTER Y REGISTER STACK POINTER PROGRAM COUNTER PROGRAM STATUS WORD Stack Address (00H ~ BFH) 15 0 8 7 SP 0
Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 00H to BFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "BF H" is used.
Figure 8-1 Configuration of Registers
Hardware fixed
Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. The Accumulator can be used as a 16-bit register with Y Register as shown below.
Y
Y A
Caution: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP
LDX TXSP #0BFH ; SP BFH
A
Two 8-bit Registers can be used as a "YA" 16-bit Register
Figure 8-2 Configuration of YA 16-bit Register
Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 8-3. It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction.
X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore).
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[Zero flag Z] This flag is set when the result of an arithmetic operation
MSB PSW NEGATIVE FLAG OVERFLOW FLAG SELECT DIRECT PAGE when g=1, page is addressed by RPR BRK FLAG
or data transfer is "0" and is cleared by any other result.
LSB
N
V
G
B
H
I
Z
C
RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT ZERO FLAG INTERRUPT ENABLE FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
[Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address. [Direct page flag G]
This flag assigns RAM page for direct addressing mode. In the direct addressing mode, addressing area is from zero page 00H to 0FFH when this flag is "0". If it is set to "1", addressing area is assigned by RPR register (address 0F3H). It is set by SETG instruction and cleared by CLRG. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127 (7FH) or -128 (80H). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag.
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GMS81C5108
At execution of a CALL/TCALL/PCALL
At acceptance of interrupt
At execution of RET instruction
At execution of RETI instruction
00BC 00BD 00BE 00BF PCL PCH Push down
00BC 00BD 00BE 00BF PSW PCL PCH Push down
00BC 00BD 00BE 00BF PCL PCH Pop up
00BC 00BD 00BE 00BF PSW PCL PCH Pop up
SP before execution SP after execution
00BF 00BD
00BF 00BC
00BD 00BF
00BC 00BF
At execution of PUSH instruction PUSH A (X,Y,PSW) 00BC 00BD 00BE 00BF A Push down
At execution of POP instruction POP A (X,Y,PSW) 00BC 00BD 00BE 00BF A Pop up 00BFH 0000H
Stack depth
SP before execution SP after execution
00BF 00BE
00BE 00BF
Figure 8-4 Stack Operation
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8.2 Program Memory
A 16-bit program counter is capable of addressing up to 64K bytes, but this device has 8K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Figure 8-5 shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 8-6. As shown in Figure 8-5, each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. Example: Usage of TCALL
LDA #5 TCALL 0FH : : ;1BYTE INSTRUCTION ;INSTEAD OF 2 BYTES ;NORMAL CALL
E000H
; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B
1
;TCALL ADDRESS AREA
PROGRAM MEMORY FEFFH FF00H FFC0H FFDFH FFE0H FFFFH TCALL AREA INTERRUPT VECTOR AREA
PCALL AREA
The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. Any area from 0FF00H to 0FFFFH, if it is not going to be used, its service location is available as general purpose Program Memory.
Address 0FFE0H Vector Area Memory Watch Timer Interrupt Vector Area Serial I/O Interrupt Vector Area AD Converter Interrupt Vector Area Remocon Interrupt Vector Area External Interrupt 2 Vector Area Timer/Counter 1 Interrupt Vector Area Timer/Counter 0 Interrupt Vector Area External Interrupt 1 Vector Area External Interrupt 0 Vector Area Basic Interval Timer Interrupt Vector Area Key Scan Interrupt Vector Area RESET Vector Area
Figure 8-5 Program Memory Map
Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 8-7.
E2 E4 E6 E8 EA EC EE F0 F2 F4 F6 F8 FA FC FE
NOTE: "-" means reserved area.
Figure 8-6 Interrupt Vector Area
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Address 0FFC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF
Program Memory TCALL 15 TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK *
Address 0FF00H
PCALL Area Memory
PCALL Area (256 Bytes)
0FFFFH
NOTE: * means that the BRK software interrupt is using same address with TCALL0.
Figure 8-7 PCALL and TCALL Memory Area
PCALL rel
4F35 PCALL 35H
TCALL n
4A TCALL 4
4F 35
4A
01001010
~ ~ ~ ~
0D125H NEXT
~ ~
Reverse
~ ~
0FF00H 0FF35H NEXT
PC: 11111111 11010110 FH FH D H 6H
0FF00H 0FFD6H 25 D1
0FFFFH
0FFD7H 0FFFFH
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Example: The usage software example of Vector address and the initialize part.
ORG DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW ORG 0FFE0H NOT_USED NOT_USED NOT_USED NOT_USED WT_INT SIO AD_Con Carrier_INT INT2 TMR1_INT TMR0_INT INT1 INT0 BIT_INT KEY_INT RESET 0F000H
; ; ; ; ; ; ; ; ; ; ; ;
Watch Timer Serial I/O AD converter Carrier Int.2 Timer-1 Timer-0 Int.1 Int.0 BIT Key Scan Reset
;******************************************** ; MAIN PROGRAM * ;******************************************** ; RESET: DI ;Disable All Interrupts CLRG LDX #0 RAM_CLR: LDA #0 ;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX #0BFH ;Stack Pointer Initialize TXSP ; CALL LCD_CLR ;Clear LCD display memory ; LDM R0, #0 ;Normal Port 0 LDM R0DR,#1000_0010B ;Normal Port Direction LDM R0PU,#1000_0010B ;Pull Up Selection Set LDM R0CR,#0000_0001B ;R0 port Open Drain control : : LDM SCMR,#1111_0000B ;System clock control : :
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8.3 Data Memory
Figure 8-8 shows the internal Data Memory space available. Data Memory is divided into four groups, a user RAM, control registers, Stack, and LCD memory. Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converters and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
PAGE0
0000H
USER MEMORY (Including STACK Area) (192 Bytes) 00BFH 00C0H 00FFH 0100H 0124H PERIPHERAL CONTROL REGISTERS LCD DISPLAY MEMORY
More detailed informations of each register are explained in each peripheral section.
Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction.
PAGE1
Example; To write at CKCTLR
LDM Figure 8-8 Data Memory Map CKCTLR,#05H ;Divide ratio /8
User Memory The GMS81C5108 has 192 x 8 bits for the user memory (RAM). There are two page internal RAM. Page is selected by Gflag and RAM page selection register RPR. When G-flag is cleared to "0", always page 0 is selected regardless of RPR value. If G-flag is set to "1", page will be selected according to RPR value.
Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. Refer to Figure 8-4 on page 20.
Page 0 RPR=0, G=0 RPR=1, G=1 Page 1 Page 0: 00~FFH Page 1: 100~124H
LCD Display Memory LCD display data area is handled in LCD section. See "19.3 LCD Display Memory" on page 73.
Figure 8-9 RAM page configuration
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Address 00C0 00C1 00C2 00C3 00C8 00C9 00CA 00CB 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 00D9 00DA 00DB 00DC 00DD 00DE 00E0
Register Name R0 port data register R1 port data register R2 port data register R3 port data register R0 port I/O direction register R1 port I/O direction register R2 port I/O direction register R3 port I/O direction register R0 port pull-up register R1 port pull-up register R2 port pull-up register R3 port pull-up register R0 port open drain control register R1 port open drain control register R2 port open drain control register R3 port open drain control register Ext. interrupt edge selection register Port selection register Interrupt enable low register Interrupt enable high register Interrupt request flag low register Interrupt request flag high register Sleep mode register Timer 0 mode register Timer 0 counter register
Symbol R0 R1 R2 R3 R0DR R1DR R2DR R3DR R0PU R1PU R2PU R3PU R0CR R1CR R2CR R3CR IESR PMR IENL IENH IRQL IRQH SMR TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWMHR ADMR ADDR
R/W R/W R/W R/W R/W W W W W W W W W W W W W R/W R/W R/W R/W R/W R/W R/W R/W R W R R/W W W R R R/W W R/W R
Initial Value
76543210
Addressing Mode byte, bit1 byte, bit byte, bit byte, bit byte2 byte byte byte byte byte byte byte byte byte byte byte byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte, bit byte, bit byte byte byte, bit byte, bit byte, bit byte byte, bit byte, bit
Page 32 32 33 33 32 32 33 33 32 32 33 33 32 32 33 33 69 32 65 65 65 65 39 45 45 45 45 45 45 45 45 45 45 45 58 58
00000000 00000000 - - - - 0000 - - - - 0000 00000000 00000000 - - - - 0000 - - - - 0000 00000000 00000000 - - - - 0000 - - - - 0000 00000000 00000000 - - - - 0000 - - - - 0000 - - 000000 - 0 - 00000 - 0000 - - - 0000000 - 0000 - - - 0000000 -------0 - - 000000 00000000 11111111 00000000 00000000 11111111 11111111 00000000 00000000 00000000 - - - - 0000 - 0 - - 0001 xxxxxxxx
00E1
Timer 0 data register Timer 0 input capture register
00E2 00E3
Timer 1 mode register Timer 1 data register PWM0 pulse period register Timer 1 counter register
00E4
Timer 1 input capture register PWM0 pulse duty register
00E5 00EC 00ED
PWM0 high register A/D converter mode register A/D converter data register
Table 8-1 Control Registers
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Address 00EF 00F0 00F1 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00FC 00FD 00FE 00FF
Register Name Watch timer mode register Key scan mode register LCD control register RAM paging register Basic interval timer register Clock control register System clock mode register Remocon mode register Carrier frequency high selection Carrier frequency low selection Remocon data high register Remocon data low register Remocon data counter Remocon output data register Remocon output buffer Buzzer data register Serial I/O mode register Serial I/O data register
Symbol WTMR KSMR LCR RPR BITR CKCTLR SCMR RMR CFHS CFLS RDHR RDLR RDC RODR ROB BDR SIOM SIOD
R/W R/W R/W R/W R/W R W R/W R/W W W W W R R/W R/W W R/W R/W
Initial Value
76543210
Addressing Mode byte, bit byte, bit byte, bit byte, bit byte, bit byte byte, bit byte, bit byte byte byte byte byte, bit byte, bit byte, bit byte byte, bit byte, bit
Page 56 70 72 73 43 43 34 76 76 76 76 76 76 76 76 60 62 62
- 0000000 00000000 00000000 - - - - - -00 00000000 - - - - 0111 00000000 - 0000000 - - 111111 - - 111111 11111111 11111111 00000000 -------0 -------0 00000000 00000001 xxxxxxxx
Table 8-1 Control Registers
1. "byte", "bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation.
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8.4 Addressing Mode
The GMS81C5108 uses six addressing modes; * Register addressing * Immediate addressing * Direct page addressing * Absolute addressing * Indexed addressing * Register-indirect addressing
35H data
(3) Direct Page Addressing dp In this mode, a address is specified within direct page. Example; G=0
C535 LDA 35H ;A RAM[35H]
~ ~
~ ~
data A
(1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm In this mode, second byte (operand) is accessed as a data immediately. Example:
0435 ADC #35H
MEMORY
0E550H 0E551H
C5 35
(4) Absolute Addressing !abs Absolute addressing sets corresponding memory data to Data, i.e. second byte (Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY Example;
0735F0 ADC !0F035H ;A ROM[0F035H]
04 35
A+35H+C A
When G-flag is 1, then RAM address is defined by 16-bit address which is composed of 8-bit RAM paging register (RPR) and 8-bit immediate data. Example: G=1, RPR=01H
E45535 LDM 35H,#55H ~ ~
0F100H 0F101H 0135H data data 55H 0F102H 07 35 F0 address: 0F035 0F035H data
~ ~
A+data+C A
0F100H 0F101H 0F102H
~ ~
E4 55 35
~ ~
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The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H regardless of G-flag and RPR.
981501 INC !0115H ;A ROM[115H]
X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; G=0, X=35H
DB LDA {X}+
115H
data
~ ~
~ ~
0F100H 0F101H 0F102H 98 15 01

data+1 data
35H
data
~ ~
data A
~ ~
DB
address: 0115
36H X
(5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H, G=1, RPR=01H
D4 LDA {X} ;ACCRAM[X].
X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; G=0, X=0F5H
C645 LDA 45H+X
115H
data
~ ~
data A
~ ~
0E550H D4
3AH
data
~ ~
0E550H 0E551H C6 45
~ ~

data A
45H+0F5H=13AH
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Y indexed direct page (8 bit offset) dp+Y This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. Y indexed absolute !abs+Y Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. Example; Y=55H
D500FA LDA !0FA00H+Y
3F35
JMP
[35H]
35H 36H
0A E3
~ ~
0E30AH NEXT
~ ~
jump to address 0E30AH
~ ~
0FA00H 3F 35
~ ~
0F100H 0F101H 0F102H
D5 00 FA
0FA00H+55H=0FA55H
X indexed indirect [dp+X] Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register data in Direct page. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, X=10H
1625 ADC [25H+X]
~ ~
0FA55H data
~ ~

data A
(6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data (or pair memory) by Operand. Also index can be used with Index register X,Y. JMP, CALL Example; G=0
0FA00H 35H 36H 05 E0
~ ~
0E005H data
~ 0E005H ~
25 + X(10) = 35H
~ ~
~ ~
16 25
A + data + C A
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Y indexed indirect [dp]+Y Processes memory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; G=0, Y=10H
1725 ADC [25H]+Y
Absolute indirect [!abs] The program jumps to address specified by 16-bit absolute address. JMP Example; G=0
1F25E0 JMP [!0E025H]
PROGRAM MEMORY
25H 26H
05 E0
0E025H 0E026H
25 E7
~ ~
0E015H data
~ ~
0E005H + Y(10) = 0E015H
~ ~
~ ~
NEXT
jump to address 0E725H
~ ~
0E725H
~ ~
0FA00H 17 25
~ ~
0FA00H 1F 25 E0
~ ~
A + data + C A
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9. I/O PORTS
The GMS81C5108 has seven ports (R0, R1, R2 and R3), and LCD segment port (SEG0~SEG36), and LCD common port (COM0~COM3). These ports pins may be multiplexed with an alternate function for the peripheral features on the device.
9.1 Registers for Port
Port Data Registers The Port Data Registers (R0, R1, R2, R3) are represented as a D-Type flip-flop, which will clock in a value from the internal bus in response to a "write to data register" signal from the CPU. The Q output of the flip-flop is placed on the internal bus in response to a "read data register" signal from the CPU. The level of the port pin itself is placed on the internal bus in response to "read data register" signal from the CPU. Some instructions that read a port activating the "read register" signal, and others activating the "read pin" signal. Port Direction Registers All pins have data direction registers which can define these ports as output or input. A "1" in the port direction register configure the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify it as input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55H" to address 0C8H (R0 port direction register) during initial setting as shown in Figure 9-1. All the port direction registers in the GMS81C5108 have 0 written to them by reset function. On the other hand, its initial status is input. pull-up port. It is connected or disconnected by Pull-up Control register (RnPU). The value of that resistor is typically 100k. Refer to DC characteristics for more details. When a port is used as key input, input logic is firmly either low or high, therefore external pull-down or pull-up resisters are required practically. The GMS81C5108 has internal pull-up, it can be logic high by pull-up that can be able to configure either connect or disconnect individually by pull-up control registers RnPU. When ports are configured as inputs and pull-up resistor is selected by software, they are pulled to high.
VDD
VDD
PULL-UP RESISTOR
PORT PIN
GND
Pull-up control bit 0: Disconnect 1: Connect
Figure 9-2 Pull-up Port Structure
WRITE "55H" TO PORT R0 DIRECTION REGISTER 0C0H 0C1H R0 DATA R1 DATA 01010101 76543210 BIT
Open drain port Registers
The R0, R1, R2 and R3 ports have open drain port resistors R0CR~R3CR. Figure 9-3 shows an open drain port configuration by control register. It is selected as either push-pull port or open-drain port by R0CR, R1CR, R2CR and R3CR.
~ ~
0C8H 0C9H R0 DIRECTION R1 DIRECTION
~ ~
IO I O I O I O PORT 76543210 I : INPUT PORT O : OUTPUT PORT
PORT PIN
Figure 9-1 Example of port I/O assignment
GND
Pull-up Control Registers The R0, R1,R2 and R3 ports have internal pull-up resistors. Figure 9-2 shows a functional diagram of a typical
Open drain port selection bit 0: Push-pull 1: Open drain
Figure 9-3 Open-drain Port Structure
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9.2 I/O Ports Configuration
R0 Ports R0 is an 8-bit CMOS bidirectional I/O port (address 0C0H). Each I/O pin can independently used as an input or an output through the R0DR register (address 0C8 H). R0 has internal pull-ups that is independently connected or disconnected by R0PU. The control registers for R0 are shown below.
R0 Data Register
R0 R07 R06 R05 R04 R03 ADDRESS : 0C0H RESET VALUE : 00H R02 R01 R00
.
Port Pin R00 R01 R02 R03 R04 R31 Alternate Function INT0 (External Interrupt 0) INT1 (External Interrupt 1) INT2 (External Interrupt 2) EC0 (Timer0 Event Input) BUZ (Buzzer Output) PWM (PWM Output)
R1 Ports R1 is an 8-bit CMOS bidirectional I/O port (address 0C1H). Each I/O pin can independently used as an input or an output through the R1DR register (address 0C9H). R1 has internal pull-ups that is independently connected or disconnected by register R1PU. If the key scan function is used, these pin can input the key switch signal without external pull-up registers. For more details refer to "18. KEY SCAN" on page 70. The control registers for R1 are shown below.
R0 Direction Register
R0DR
ADDRESS : 0C8H RESET VALUE : 00H
Port Direction 0: Input 1: Output
R0 Pull-up Selection Register
R0PU
ADDRESS :0D0H RESET VALUE : 00H Pull-up select 0: Without pull-up 1: With pull-up
R0 Open Drain Selection Register
R0CR
R1 Data Register
ADDRESS :0D4H RESET VALUE : 00H Open Drain select 0: No Open Drain 1: Open Drain ADDRESS :0D9H RESET VALUE : -0-00000B BUZ EC0 INT2 INT1 INT0
ADDRESS : 0C1H RESET VALUE : 00H R15 R14 R13 R12 R11 R10
R1
R17
R16
R1 Direction Register
R1DR
ADDRESS : 0C9H RESET VALUE : 00H
Port Mode Register
PMR PWMO
Port Direction 0: Input 1: Output
PWMO (PWM Output) 0: R31 Port 1: PWM EC0 (Timer0 Event Input) 0: R03 Port 1: EC0 INT1 (External Interrupt) 0: R01 Port 1: INT1
BUZ (Buzzer Output) 0: R04 Port 1: BUZ INT2 (External Interrupt) 0: R02 Port 1: INT2 INT0 (External Interrupt) 0: R00 Port 1: INT0
R1 Pull-up Selection Register
R1PU
ADDRESS : 0D1H RESET VALUE : 00H
Pull-up select 0: Without pull-up 1: With pull-up
R1 Open Drain Selection Register
R1CR
ADDRESS :0D5H RESET VALUE : 00H
In addition, Port R0 and R3 are multiplexed with various special features. The control register PMR (address 0D9H) controls the selection of alternate function. After reset, this value is "0", port may be used as normal I/O port. To use alternate function such as External Interrupt rather than normal I/O, write "1" in the corresponding bit of PMR0.
Open Drain select 0: No Open Drain 1: Open Drain
KEY SCAN Mode Register
KSMR
ADDRESS :0F0H RESET VALUE : 00H
KEY Input select 0: Port selection 1: KS selection
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Port R1 is multiplexed with various special features.The control registers controls the selection of alternate function. After reset, this value is "0", port may be used as normal I/O port. The way to select alternate function such as comparator input or buzzer will be shown in each peripheral section. In addition, R1 port is used as key scan function which operate with normal input port. Input or output is configured automatically by each function register (KSMR) regardless of R1DR. R2 Port R2 is a 4-bit CMOS bidirectional I/O port (address 0C2H). Each I/O pin can independently used as an input or an output through the R2DR register (address 0CAH). R2 has internal pull-ups that is independently connected or disconnected by R2PU (address 0D2 H). The control registers for R2 are shown as below.
ADDRESS: 0C2H RESET VALUE: ----0000B R23 R22 R21 R20
R3 Port R3 is a 4-bit CMOS bidirectional I/O port (address 0C3H). Each I/O pin can independently used as an input or an output through the R3DR register (address 0CBH).
R3 Data Register
R3 -
ADDRESS: 0C3H RESET VALUE: ----0000B R33 R32 R31 R30
R3 Direction Register
R3DR -
ADDRESS : 0CBH RESET VALUE : ----0000B
Port Direction 0: Input 1: Output
R3 Pull-up Selection Register
R3PU -
ADDRESS : 0D3H RESET VALUE : ----0000B
R2 Data Register
R2 -
Pull-up select 0: Without pull-up 1: With pull-up
R3 Open Drain Selection Register
R3CR -
ADDRESS : 0D7H RESET VALUE : ----0000B
R2 Direction Register
R2DR -
ADDRESS : 0CAH RESET VALUE : ----0000B
Port Direction 0: Input 1: Output
Pull-up select 0: No Open Drain 1: Open Drain
R2 Pull-up Selection Register
R2PU -
SEG0~SEG36
ADDRESS : 0D2H RESET VALUE : ----0000B
Segment signal output pins for the LCD display. See "19. LCD DRIVER" on page 71 for details. COM0~COM3 Common signal output pins for the LCD display. See "19. LCD DRIVER" on page 71 for details. SEG34~SEG36 and COM1~COM3 are selected by LCDD of the LCR register.
Pull-up select 0: Without pull-up 1: With pull-up
R2 Open Drain Selection Register
R2CR -
ADDRESS : 0D6H RESET VALUE : ----0000B
Pull-up select 0: No Open Drain 1: Open Drain
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10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and the peripheral hardware. It contains two oscillators: a main-frequency clock oscillator and a sub-frequency clock oscillator. Power consumption can be reduced by switching them to the low power operation frequency clock can be easily obtained by attaching a resonator between the XIN and XOUT pin and the SXIN and SXOUT pin, respectively. The system clock can also be obtained from the external oscillator. The clock generator produces the system clocks forming clock pulse, which are supplied to the CPU and the peripheral hardware. The internal system clock can be selected by bit2, and bit3 of the system clock mode register (SCMR). The registers are shown in Figure 10-2.
Instruction cycle time CPU clock /2 /8 / 16 / 64 fMAIN = 4MHz 0.5 us 2.0 us 4.0 us 16.0 us fSUB = 32.768kHz 61 us 244 us 488 us 1953 us
To the peripheral block, the clock among the not-divided original clocks, divided by 2, 4,..., up to 1024 can be provided. Peripheral clock is enabled or disabled by STOP instruction. The peripheral clock is controlled by clock control register (CKCTLR). See "11. BASIC INTERVAL TIMER" on page 43 for details.
SYCC<1> SYCC<0>
** Clock is frozen by STOP or SLEEP[SMR.0] Instruction. ** Clock is released 1) by BIT overflow when previos state has been STOP mode. 2) by interrupts when previos state has been SLEEP mode. SLEEP Mode SCS[1:0] select clock
STOP Mode
OSC Stop PRESCALER
/2 /8 /16 /64 MUX
XIN SXIN
0 1
Internal system clock
PRESCALER
PS0 PS1 PS2 PS3 PS4 PS5 PS6 PS7 PS8 PS9 PS10
/1
/2
/4
/8
/16
/32
/64
/128
/256
/512 /1024
Peripheral clock
fEX (Hz)
Frequency 4M period
PS0 4M 250n
PS1 2M 500n
PS2 1M 1u
PS3 500K 2u
PS4 250K 4u
PS5 125K 8u
PS6 62.5K 16u
PS7 31.25K 32u
PS8 15.63K 64u
PS9 7.183K 128u
PS10 3.906K 256u
Figure 10-1 Block Diagram of Clock Generator
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The system clock is decided by bit1 of the system clock mode register, SCMR. In selection Sub clock, to oscillate or stop the Main clock is decided by bit0 of SCMR.
SCMR (System Clock Mode Register)
MSB R/W R/W R/W R R/W R/W R/W
On the initial reset, internal system clock is PS1 which is the fastest and other clock can be provided by bit2 and bit3 of SCMR.
LSB R/W
ADDRESS: 0F5H INITIAL VALUE: 00H SYCC[1:0] (System clock control) 00: main clock on 01: main clock on 10: sub clock on (main clock on) 11: sub clock on (main clock off) SCS[1:0] (System clock source select) 00: fMAIN/2 or fSUB/2 01: fMAIN/8 or fSUB/8 10: fMAIN/16 or fSUB/16 11: fMAIN/64 or fSUB/64
SVD[1:0] (SVD Flag) SVD0 : set at VDD=2.2V SVD1 : set at VDD=1.7V SVRT (System Reset Control by SVD1 Bit) 0 : System reset by SVD1 Flag 1 : Don't system reset by SVD1 Flag (Freeze) SVEN (SVD Operation Enable Bit) 0 : SVD Operation Enable 1 : SVD Operation Disable
* The values of 1.7V and 2.2V could be changed by 0.2V according to the process of work.
Figure 10-2 SCMR : System Clock Control Registers
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10.1 Operation Mode
The system clock controller starts or stops the main-frequency clock oscillator and switches between the sub frequency clock. The operating mode is generally divided into the main active mode and the sub active mode, which are controlled by System clock mode register (SCMR). Figure 10-3 shows the operating mode transition diagram. System clock control is performed by the system clock mode register, SCMR. During reset, this register is initialized to "0" so that the main-clock operating mode is selected. Main Active mode This mode is fast-frequency operating mode. The CPU and the peripheral hardwares are operated on the high-frequency clock. At reset release, this mode is invoked. Sub Active mode This mode is low-frequency operating mode In this mode, the CPU and the peripheral hardware clock are provided by low-frequency clock oscillation, so power consumption can be reduced. SLEEP mode In this mode, the CPU clock stops while peripherals and the oscillation source continue to operate normally. STOP mode In this mode, the system operations are all stopped, holding the internal states valid immediately before the stop at the low power consumption level.
Main : Oscillation Sub : Oscillation System Clock : Main
Main : Oscillation Sub : Oscillation System Clock : Sub
Main Active Mode
e3 ot *N
SET1 SCMR.1 CLR1 SCMR.1
/N ot e2
Sub Active Mode 1
* Note1 : Stop released by Reset, Key Scan Watch Timer interrupt Timer interrupt (event counter) SIO (External clock) External interrupt * Note2 : Sleep released by Reset, Key Scan All interrupts * Note3 : this is sequential 1) CLR1 SCMR.0 2) Oscillation stabilation time (more than 65ms) 3) CLR1 SCMR.1 - Sub clock cannot be stopped by STOP instruction.
STOP / SET1 SMR.0
* Note1 / * Note2
*N
ot e1
SET1 SCMR.0
CLR1 SCMR.0
SM
R .0
M LD
/( ** 1) SE T1
SC R M H 03 ,#
ST
O P
Stop / Sleep Mode
* Note1 / * Note2 STOP / SET1 SMR.0
Sub Active Mode 2
Main : Stop or Oscillation (case of **1) Sub : Oscillation System Clock : Stop
Main : Stop Sub : Oscillation System Clock : Sub
Figure 10-3 Operating Mode
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10.2 Operation Mode Switching
In the Main active mode, only the high-frequency clock oscillator is used. In the Sub active mode, the low-frequency clock oscillation is used, so the low power voltage operation or the low power consumption operation can be enabled. Instruction execution does not stop during the change of operation mode. In this case, some peripheral hardware capabilities may be affected. For details, refer to the description of the relevant operation. The following describes the switching between the Main active mode and the Sub active mode. During reset, the system clock mode register is initialized at the Main active mode. It must be set to the Sub active mode for reducing the power consumption. Switching from Main active to Sub active First, write "02H" into lower 2 bits of SCMR to switch the main system clock to the sub-frequency clock. Next, write "03H" to turn off main frequency oscillation. Example:
: : : LDM LDM : : : : :
;about 65ms software delay DELAY: LDA #0 DELAY0: INC A CMP #85H BCC DELAY0 RET
Shifting from the Normal operation to the SLEEP mode By setting bit 0 of SMR, the CPU clock stops and the SLEEP mode is invoked. The CPU stops while other peripherals are operate normally. The way of release from this mode is RESET and all available interrupts. For more detail, See " SLEEP Mode" on page 39 Shifting from the Normal operation to the STOP mode
SCMR,#02H SCMR,#03H
;Switch to sub active ;Turn off main clock
By executing STOP instruction, the main-frequency clock oscillation stops and the STOP mode is invoked. But subfrequency clock oscillation is operated continuously. After the STOP operation is released by reset, the operation mode is changed to Main active mode. The methods of release are RESET, Key scan interrupt, Watch Timer interrupt, Timer/Event counter1 (EC0 pin), SIO (External clock) and External Interrupt. For more details, see " STOP Mode" on page 40.
Note: In the STOP and SLOW operating modes, the power consumption by the oscillator and the internal hardware is reduced. However, the power for the pin interface (depending on external circuitry and program) is not directly associated with the low-power consumption operation. This must be considered in system design as well as interface circuit design.
Returning from Sub active to Main active First, write "02H" into lower 2 bits of the SCMR to turn on the main-frequency oscillation. This time, the stabilization (warm-up) time needs to be taken by the software delay routine. Sub active mode can also be released by setting the RESET pin to low, which immediately performs the reset operation. After reset, the GMS81C5108 is placed in Main active mode. Example:
: : : LDM SCMR,#02H CALL DELAY LDM SCMR,#0
;Turn on main-clock ;Wait until stable ;Move to main active
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~ ~
Main freq. clock (XIN pin) Sub freq. clock (SXIN pin)
~ ~ ~ ~ ~ ~
Operation clock
Main-clock operation
Changed to the Sub-clock SCMR XXXX XX10B Turn off main clock SCMR XXXX XX11B
(a) Main active mode Sub active mode
~ ~
Sub-clock operation
~ ~
Main freq. clock (XIN pin)
Stabilizing Time > 60ms
~ ~ ~ ~
Sub freq. clock (SXIN pin)
Operation clock
~ ~
Sub-clock operation Main-clock operation
Changed to the Transition SCMR XXXX XX10B
Changed to the Main-clock SCMR XXXX XX00B or XXXX XX01B
(b) Sub active mode Main active mode
Figure 10-4 System Clock Switching Timing
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10.3 Power Saving Operation
GMS81C5108 has 2 power-saving mode. In power-saving mode, power consumption is reduced considerably that in Battery operation Battery life can be extended a lot. Sleep mode is entered by setting bit 0 of Sleep Mode Register (SMR), and STOP Mode is entered by STOP instruction. SLEEP Mode In this mode, the internal oscillation circuits remain active. Oscillation continues and peripherals are operate normally but CPU stops. Movement of all Peripherals is shown in Table 10-1. Sleep mode is entered by setting bit 0 of SMR (address 0DEH).
0: Release Sleep Mode 1: Enter Sleep Mode
It is released by RESET or interrupt. To be released by interrupt, interrupt should be enabled before Sleep mode.
Sleep Mode Register SMR -
ADDRESS : 0DEH RESET VALUE : -------0B -
Figure 10-5 SLEEP Mode Register
Oscillator (XIN or SXIN pin) Internal CPU Clock
~ ~ ~ ~
Interrupt
Set bit 0 of SMR Release
Normal Operation
Stand-by Mode
Normal Operation
Figure 10-6 Sleep Mode Release Timing by External Interrupt
.
Oscillator (XIN or SXIN pin)
~ ~
~ ~
Internal CPU Clock
~ ~
~~ ~~
RESET
Set bit 0 of SMR
Release
~~ ~~
~~ ~~
BIT Counter
0
1
2
FE
FF
0
1
2
Clear & Start Normal Operation Stand-by Mode
tST = 62.5ms Normal Operation at 4.19MHz by hardware tST = 1 fMAIN /1024 x 256
Figure 10-7 SLEEP Mode Release Timing by RESET pin
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STOP Mode For applications where power consumption is a critical factor, device provides STOP mode for reducing power consumption. Start The Stop Operation The STOP mode can be entered by STOP instruction durPeripheral CPU RAM LCD driver Basic Interval Timer Timer/Event counter 0,1 Watch Timer Key Scan Main-oscillation Sub-oscillation I/O ports Control Registers Release method STOP Mode All CPU operations are disabled Retain Operates continuously Halted
ing program execution. In Stop mode, the on-chip mainfrequency oscillator, system clock, and peripheral clock are stopped (Watch timer clock is oscillating continuously:. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins output the values held by their respective port data register, the port direction registers. The status of peripherals during Stop mode is shown below.
Sleep Mode All CPU operations are disabled Retain Operates continuously Operates continuously Timer/Event counter 0,1 operates continuously Operates continuously Active Oscillation1 Oscillation Retain Retain by RESET, All interrupts
Halted (Only when the Event counter mode is enabled, Timer 0,1 operates normally) Operates continuously Active Stop (XIN=L, XOUT=L) Oscillation Retain Retain by RESET, Key Scan interrupt, SIO interrupt, Watch Timer interrupt, Timer interrupt (EC0), and External interrupt
Table 10-1 Peripheral Operation during Power Saving Mode
1. refer to the Table 10-2
Operating Clock source Main Clock Sub Clock System Clock Peri. Clock
Main Operating Mode Oscillation Oscillation Active Active
Main Sleep Mode Oscillation Oscillation Stop Active
Sub Operating Mode SCMR<1:0> 00,01,10 Oscillation 11 Stop Oscillation Active Active
Sub Sleep Mode SCMR<1:0> 00,01,10 Oscillation 11 Stop Oscillation Stop Active
Stop Mode
Stop Oscillation Stop Stop
Table 10-2 Clock Operation of STOP and SLEEP mode
Note: Since the XIN pin is connected internally to GND to avoid current leakage due to the crystal oscillator in STOP mode, do not use STOP instruction when an external clock is used as the main system clock.
is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level before the Stop mode is terminated. The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. And after STOP instruction, at least two or more NOP instruction should be written as shown in example below.
In the Stop mode of operation, VDD can be reduced to minimize power consumption. Be careful, however, that VDD
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Example)
: LDM STOP NOP NOP : CKCTLR,#0000_1111B
The Interval Timer Register CKCTLR should be initialized by software in order that oscillation stabilization time should be longer than 20ms before STOP mode. Release the STOP mode The exit from STOP mode is using hardware reset or external interrupt, watch timer, SIO interrupt, key scan or timer interrupt (EC0).
To release STOP mode, corresponding interrupt should be enabled before STOP mode. Specially as a clock source of Timer/Event counter, EC0 pin can release it by Timer/Event counter Interrupt request Reset redefines all the control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. Start-up is performed to acquire the time for stabilizing oscillation. During the start-up, the internal operations are all stopped.
Oscillator (XIN pin) Internal Clock External Interrupt
~~ ~~
STOP Instruction Executed
~~ ~~ ~ ~ ~~ ~~
~ ~ ~ ~ ~~ ~~
BIT Counter
n
n+1 n+2
n+3
0 Clear
1
FE
FF
0
1
2
Normal Operation
Stop Operation
tST > 20ms by software
Normal Operation
Before executing Stop instruction, Basic Interval Timer must be set properly by software to get stabilization time which is longer than 20ms.
Figure 10-8 STOP Mode Release Timing by External Interrupt
Oscillator (XIN pin) Internal Clock
~~ ~~
~ ~ ~ ~
~ ~~ ~
RESET BIT Counter
~ ~
STOP Instruction Executed n n+1 n+2 n+3 n+4
~~ ~~
Normal Operation
Stop Operation
Figure 10-9 STOP Mode Release Timing by RESET
~~ ~~
0 Clear
1
FE
FF
0
1
2
Normal Operation tST > 62.5ms at 4.19MHz by hardware 1 fMAIN /1024
tST =
x 256
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Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical.
Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the highimpedance state, a current flow across the ports input transistor, requiring it to fix the level by pull-up or other means.
It should be set properly that current flow through port doesn't exist. First consider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if unfirmed voltage level (not VSSor VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-saving register, it is set to low.
INPUT PIN INPUT PIN internal pull-up OPEN VDD VDD i=0
VDD
VDD
O
i GND VDD
i
O
i=0 GND
Very weak current flows
X
Weak pull-up current flows
X
OPEN
O
When port is configured as an input, input level should be closed to 0V or VDD to avoid power consumption.
O
Figure 10-10 Application Example of Unused Input Port
OUTPUT PIN ON OPEN ON OFF i GND ON VDD OFF
OUTPUT PIN VDD L ON OFF i GND ON i=0 GND L VDD
O
OFF
X
OFF
X O
O
In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port.
In the left case, much current flows from port to GND.
Figure 10-11 Application Example of Unused Output Port
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11. BASIC INTERVAL TIMER
The GMS81C5108 has one 8-bit Basic Interval Timer that is free-run and can not stop. Block diagram is shown in Figure 11-1. The Basic Interval Timer Register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. After reset, the BCK bits are all set, so the longest oscillation stabilization time is obtained. It also provides a Basic interval timer interrupt (BITF). The count overflow of BITR from FFH to 00H causes the interrupt to be generated. The Basic Interval Timer is controlled by the clock control register (CKCTLR) shown in Figure 11-2. Source clock can be selected by lower 3 bits of CKCTLR. When write "1" to bit BCL of CKCTLR, BITR register is cleared to "0" and restart to count up. The bit BCL becomes "0" automatically after one machine cycle by hardware. BITR and CKCTLR are located at same address, and address 0F4H is read as a BITR, and written to CKCTLR.
fMAIN/23 fMAIN/24 fMAIN/25 fMAIN/26 fMAIN/27 fMAIN/28
fMAIN/29 or fSUB/29 fMAIN/210 or fSUB/210 Select Input clock BCK<2:0> fMAIN: main-clock frequency fSUB: sub-clock frequency [0F4H] Basic Interval Timer clock control register
or fSUB/23 or fSUB/24 or fSUB/25 or fSUB/26 or fSUB/27 or fSUB/28
MUX
source clock
8-bit up-counter overflow
BITR
[0F4H]
BITF
Basic Interval Timer Interrupt
clear 3
BCL
CKCTLR
Internal bus line
Figure 11-1 Block Diagram of Basic Interval Timer
Source clock BCK <2:0> 000 001 010 011 100 101 110 111 SCM R[1:0]= 00 or 01 fMAIN/23 fMAIN/24 fMAIN/25 fMAIN/26 fMAIN/27 fMAIN/28 fMAIN/29 fMAIN/210 SCM R[1:0]= 10 or 11 fSUB/23 fSUB/24 fSUB/25 fSUB/26 fSUB/27 fSUB/28 fSUB/29 fSUB/210
Interrupt (overflow) Period At fMAIN=4MHz 0.512 ms 1.024 2.048 4.096 8.192 16.384 32.768 65.536 At fSUB=32.768kHz 62.5 ms 125.0 250.0 500.0 1000.0 2000.0 4000.0 8000.0
Table 11-1 Basic Interval Timer Interrupt Time
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CKCTLR
7 -
6 -
5 -
4 -
3 2 1 0 BCL BCK2 BCK1 BCK0
ADDRESS: 0F4H INITIAL VALUE: ----0111B
Caution:
Both register are in same address, when write, to be a CKCTLR, when read, to be a BITR.
Basic Interval Timer source clock select 000: fMAIN/23 or fSUB/23 001: fMAIN/24 or fSUB/24 fMAIN: main-clock frequency 010: fMAIN/25 or fSUB/25 fSUB: sub-clock frequency 011: fMAIN/26 or fSUB/26 100: fMAIN/27 or fSUB/27 101: fMAIN/28 or fSUB/28 110: fMAIN/29 or fSUB/29 111: fMAIN/210 or fSUB/210 Clear bit 0: Normal operation (free-run) 1: Clear 8-bit counter (BITR) to "0". This bit becomes 0 automatically after one machine cycle. 5 4 3 2 1 0
7
6
BITR
8-BIT BINARY COUNTER
ADDRESS: 0F4H INITIAL VALUE: 00H
Figure 11-2 BITR: Basic Interval Timer Mode Register Example 1: Interrupt request flag is generated every 8.192ms at 4MHz. : LDM SET1 EI : CKCTLR,#0CH BITE
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12. Timer / Counter
Timer/Event Counter consists of prescaler, multiplexer, 8bit timer data register, 8-bit counter register, mode register, input capture register and Comparator as shown in Figure 12-3. And the PWM high register for PWM is consisted separately. The timer/counter has seven operating modes. - 8 Bit Timer/Counter Mode - 8 Bit Capture Mode - 8 Bit Compare Output Mode - 16 Bit Timer/Counter Mode - 16 Bit Capture Mode - 16 Bit Compare Output Mode - PWM Mode In the "timer" function, the register is increased every internal clock input. Thus, one can think of it as counting inExample 1: Timer 0 = 8-bit timer mode, 8ms interval at 4MHz Timer 1 = 8-bit timer mode, 4ms interval at 4MHz LDM LDM LDM LDM LDM SET1 SET1 EI : : : SCMR,#0 ;Main clock mode TDR0,#249 TM0,#0001_0011B TDR1,#124 TM1,#0000_1111B T0E T1E
ternal clock input. Since a least clock consists of 2 and most clock consists of 1024 oscillator periods, the count rate is 1/2 to 1/1024 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source (1/1 to 1/8). In the "counter" function, the register is increased in response to a 0-to-1 (rising edge) transition at its corresponding external input pin EC0 (Timer 0). In addition the "capture" function, the register is increased in response external interrupt same with timer function. When external interrupt edge input, the count register is captured into capture data register CDRx. Timer1 is shared with "PWM" function and "Compare output" function.
Example 3: Timer0 = 8-bit event counter, 2ms interval at 4MHz Timer1 = 8-bit capture mode, 2us sampling count. LDM LDM LDM LDM LDM LDM LDM SET1 SET1 SET1 EI : TDR0,#99 ;99+1, 100 count TM0,#01FH ;event counter R0DR,#XXXX_1XXXB ;R03input IESR,#XXXX_01XXB PMR,#XXXX_1X1XB TDR1,#0FFH TM1,#0001_1011B ;FALLING ;EC0,INT1 ;2us
T0E;ENABLE TIMER 0 T1E;ENABLE TIMER 1 INT1E;ENABLE EXT. INT1
X: don't care. Example 2: Timer0 = 16-bit timer mode, 0.5s at 4MHz LDM LDM LDM LDM LDM SET1 EI : : : SCMR,#0 TDR0,#23H TDR1,#0F4H TM0,#0FH TM1,#4CH T0E ;Main clock mode ;FMAIN/32, 8us Example 4: Timer0 = 16-bit capture mode, 8us sampling count. at 4MHz LDM LDM LDM LDM LDM LDM SET1 SET1 EI : TDR0,#0FFH TDR1,#0FFH TM0,#02FH TM1,#04FH IESR,#XXXX_XX01B PMR,#XXXX_XXX1B ;AS INT0
T0E;ENABLE TIMER 0 INT0E;ENABLE EXT. INT0
X: don't care.
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TM0 (Timer0 Mode Register)
Bit : 7 6 R/W 5 CAP0 R/W 4 T0CK2 R/W 3 T0CK1 R/W 2 T0CK0 R/W 1 T0CN R/W 0 T0ST ADDRESS: 0E0H INITIAL VALUE:--000000B
Reserved CAP0 (Capture Mode Selection Bit) 0: Capture Disable 1: Capture Enable T0CN (Timer 0 Continue Start) 0: Stop Counting 1: Start Counting T0ST (Timer 0 Start Control) 0: stop counting 1: clear the counter and start count again T0CK[2:0] (Timer 0 Input Clock Selection) 000: fMAIN/2 or fSUB/2 001: fMAIN/22 or fSUB/22 010: fMAIN/23 or fSUB/23 011: fMAIN/25 or fSUB/25 fMAIN: main-clock frequency 100: fMAIN/27 or fSUB/27 fSUB: sub-clock frequency 9 9 or f 101: fMAIN/2 SUB/2 10 10 or f 110: fMAIN/2 SUB/2 111: External Event clock (EC0)
TM1 (Timer1 Mode Register)
Bit : R/W 7 POL R/W 6 16BIT R/W 5 PWME R/W 4 CAP1 R/W 3 T1CK1 R/W 2 T1CK0 R/W 1 T1CN R/W 0 T1ST ADDRESS: 0E2H INITIAL VALUE:00000000B
POL (PWM Output Polarity Selection) 0: Duty Active Low 1: Duty Active High 16BIT (16 Bit Mode Selection) 0: 8-Bit Mode 1: 16-Bit Mode PWME (PWM Enable Bit) 0: PWM Disable 1: PWM Enable CAP1 (Capture Mode Selection Bit) 0: Capture Disable 1: Capture Enable
T1CK[1:0] (Timer 1 Input Clock Selection) or fSUB 00: fMAIN 01: fMAIN/2 or fSUB/2 10: fMAIN/23 or fSUB/23 11: Timer 0 Clock T1CN (Timer 1 Continue Start) 0: Stop Counting 1: Start Counting T1ST (Timer 1 Start Control) 0: stop counting 1: clear the counter and start count again
**The counter will be cleared and restarted only when the TxST bit cleared and set again. If TxST bit set again when TxST bit is set, the counter can't be cleared but only start again.
Figure 12-1 Timer0,1 Registers
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CDR0 (Input Capture Register) T0 (Timer 0 Counter Register)
Bit : R 7 CDR07 R 6 CDR06 R 5 CDR05 R 4 CDR04 R 3 CDR03 R 2 CDR02 R 1 CDR01 R 0 CDR00 ADDRESS: E1H INITIAL VALUE:00H
In Timer mode, this register is the value of Timer 0 counter and in Capture mode, this register is the value of input capture.
TDR0 (Timer 0 Data Register)
Bit : W 7 TDR07 W 6 TDR06 W 5 TDR05 W 4 TDR04 W 3 TDR03 W 2 TDR02 W 1 TDR01 W 0 TDR00 ADDRESS: 0E1H INITIAL VALUE:FFH
If the counter of Timer 0 and the data of TDR0 is equal, interrupt is occurred.
CDR1 (Input Capture Register) T1 (Timer 1 Counter Register)
Bit : R 7 CDR17 R 6 CDR16 R 5 CDR15 R 4 CDR14 R 3 CDR13 R 2 CDR12 R 1 CDR11 R 0 CDR10 ADDRESS: 0E4H INITIAL VALUE:00H
In Timer mode, this register is the value of Timer 1 counter and in Capture mode, this register is the value of input capture.
TDR1 (Timer 1 Data Register)
Bit : W 7 TDR17 W 6 TDR16 W 5 TDR15 W 4 TDR14 W 3 TDR13 W 2 TDR12 W 1 TDR11 W 0 TDR10 ADDRESS: 0E3H INITIAL VALUE:FFH
If the counter of Timer 1 and the data of TDR1 is equal, interrupt is occurred.
T1PPR (Timer 1 Pulse Period Register)
Bit : W 7 W 6 W 5 W 4 W 3 W 2 W 1 W 0 ADDRESS: 0E3H INITIAL VALUE:FFH
T1PPR7 T1PPR6 T1PPR5 T1PPR4 T1PPR3 T1PPR2 T1PPR1 T1PPR0
The period is decided by PWM.
T1PDR (Timer 1 Pulse Duty Register)
Bit : W/R 7 W/R 6 W/R 5 W/R 4 W/R 3 W/R 2 W/R 1 W/R 0 ADDRESS: 0E4H INITIAL VALUE:00H
T1PDR7 T1PDR6 T1PDR5 T1PDR4 T1PDR3 T1PDR2 T1PDR1 T1PDR0
In PWM mode, decide the pulse duty.
PWMHR (PWM High Register)
Bit : 7 6 5 4 W 3 W 2 W 1 W 0 PWM03 PWM02 PWM01 PWM00 ADDRESS: 0E5H INITIAL VALUE:----0000B
Reserved
PWM Period = [PWMHR[3:2] + T1PPR] x Source Clock PWM Duty = [PWMHR[1:0] + T1PDR] x Source Clock
Figure 12-2 Related Registers with Timer/Counter
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16BIT 0 0 0 0 1 1 1 1
CAP0 0 0 1 0 0 0 1 0
CAP1 0 1 0 0 0 0 X1 0
PWME 0 0 0 1 0 0 0 0
T0CK[2:0] T1CK[1:0] XXX 111 XXX XXX XXX 111 XXX XXX XX XX XX XX 11 11 11 11
PWMO 0 0 1 1 0 0 0 1
Timer 0 8 Bit Timer 8 Bit Event Counter 8 Bit Capture 8 Bit Timer/Counter 16 Bit Timer 16 Bit Event Counter 16 Bit Capture 16 Bit Compare Output
Timer 1 8 Bit Timer 8 Bit Capture 8 Bit Compare Output 10 Bit PWM
1. X: The value "0" or "1" corresponding your operation.
Table 12-1 Operating Modes of Timer 0 and Timer 1
12.1 8-Bit Timer/Counter Mode
The GMS81C5108 has two 8-bit Timer/Counters, Timer 0, Timer 1, as shown in Figure 12-3. The "timer" or "counter" function is selected by mode registers TMx as shown in Figure 12-1 and Table 12-1. To use as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to "0" and bits 16BIT of TM1 should be cleared to "0" (Table 12-1 ).
TM0
-
-
CAP0 0
T0CK2 X CAP1 0
T0CK1 X T1CK1 X
T0CK0 X T1CK0 X
T0CN X T1CN X
T0ST X T1ST X
ADDRESS : 0E0H RESET VALUE : --000000B
TM1
POL X
16BIT 0
PWME 0
ADDRESS : 0E2H RESET VALUE : 00000000B
X : The value "0" or "1" corresponding your operation.
T0CK[2:0] Edge Detector EC0
1
T0ST 0 : Stop 1 : Clear and Start MUX T0 (8-bit) CLEAR
XIN SXIN
2
0X 1X
SCMR[1:0]
/2 /4 /8 / 32 / 128 / 512 / 1024 /1 /2 /8
T0IF T0CN TDR0 (8-bit) T1CK[1:0] T1ST 0 : Stop 1 : Clear and Start
1
TIMER 0 INTERRUPT
COMPARATOR
[PMR.6] PWMO
MUX
T1 (8-bit)
CLEAR
F/F COMPO PIN (R31) T1IF TIMER 1 INTERRUPT
T1CN TDR1 (8-bit)
COMPARATOR
Figure 12-3 Block Diagram of Timer/Event Counter
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These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 1024 (selected by control bits T0CK2, T0CK1 and T0CK0 of register TM0) and 1, 2, 8 (selected by control bits T1CK1 and T1CK0 of register TM1). In the Timer, timer register TX increases from 00H until it matches TDRX and then reset to 00H. If the value of TX is equal with TDRX, Timer X interrupt is occurred (latched in TXIF bit). TDR0 and T0 register are in same address, so this register is read from T0 and written to TDR0.
TDR0
n n-1
up -c ou nt
In counter function, the counter is increased every 0-to 1 (rising edge) transition of EC0 pin. In order to use counter function, the bit R03 of the R0 Direction Register (R0DR) should be set to "0" and the bit EC0 of Port Mode Register (PMR) should set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not used as a counter.
Note: The contents of TDR0 and TDR1 must be initialized (by software) with the value between 1H and 0FFH, not 0H.
9 8 7 6
PCP
~ ~
~ ~
~ ~
2 1 0
5 4 3
TIME
Interrupt period = PCP x (n+1)
Timer 0 (T0IF) Interrupt
Occur interrupt
Occur interrupt
Occur interrupt
Figure 12-4 Counting Example of Timer Data Registers
TDR0
disable enable
clear & start stop
up -c ou nt
~ ~
~ ~
TIME Timer 0 (T0IF) Interrupt
Occur interrupt Occur interrupt
T0ST Start & Stop
T0ST = 0
T0ST = 1
T0CN Control count
T0CN = 0 T0CN = 1
Figure 12-5 Timer Count Operation
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12.2 16 Bit Timer/Counter Mode
The Timer register is running with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000H until it matches TDR0, TDR1 and then resets to 0000 H . The match output generates Timer 0 interrupt not Timer 1 interrupt. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0. In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively.
TM0
-
-
CAP0 0
T0CK2 X
T0CK1 X
T0CK0 X
T0CN X
T0ST X
ADDRESS : 0E0H RESET VALUE : --000000B
TM1
POL X
16BIT 1
PWME 0
CAP1 0
T1CK1 1
T1CK0 1
T1CN X
T1ST X
ADDRESS : 0E2H RESET VALUE : 00000000B
X : The value "0" or "1" corresponding your operation.
T0CK[2:0] Edge Detector EC0
1
T0ST 0 : Stop 1 : Clear and Start
XIN SXIN
2
0X 1X
SCMR[1:0]
/2 /4 /8 / 32 / 128 / 512 / 1024
MUX
T1 (8-bit)
T 0 (8 -b it)
CLEAR
T0CN COMPARATOR F/F TDR1 (8-bit) TDR0 (8-bit)
T0IF
TIMER 0 INTERRUPT
COMPO (R31) PWMO [PMR.6]
Figure 12-6 16-bit Timer / Counter Mode
12.3 8-Bit Capture Mode
The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 12-7. As mentioned above, not only Timer 0 but Timer 1 can also be used as a capture mode. The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when timer register T0 (T1) increases and matches TDR0 (TDR1). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 12-9, the pulse width of captured signal is wider than the timer data value (FF H ) over 2 times. When external interrupt is occurred, the captured value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurrence. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be captured into registers CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IESR (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt.
Note: The CDR0, TDR0 and T0 are in same address. In the capture mode, reading operation is read the CDR0 and in timer mode, reading operation is read the T0. TDR0 is only for writing operation. The CDR1, T1 are in same address, the TDR1 is located in different address. In the capture mode, reading operation is read the CDR1
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TM0
-
-
CAP0 1
T0CK2 X
T0CK1 X
T0CK0 X
T0CN X
T0ST X
ADDRESS : 0E0H RESET VALUE : --000000B
TM1
POL X
16BIT 0
PWME 0
CAP1 1
T1CK1 X
T1CK0 X
T1CN X
T1ST X
ADDRESS : 0E2H RESET VALUE : 00000000B
T0CK[2:0] Edge Detector EC0
1
T0ST 0 : Stop 1 : Clear and Start CLEAR
XIN SXIN
2
0X 1X
SCMR[1:0] INT0
/2 /4 /8 / 32 / 128 / 512 / 1024
MUX
T0 (8-bit)
T0IF T0CN CAPTURE CDR0 (8-bit) COMPARATOR TDR0 (8-bit)
TIMER 0 INTERRUPT
INT0IF T0ST 0 : Stop 1 : Clear and Start
1
INT 0 INTERRUPT
IESR[1:0]
/1 /2 /8
MUX
T1 (8-bit)
CLEAR
T1IF T1CK[1:0] IESR[3:2] CDR1 (8-bit) CAPTURE INT1 INT1IF TDR1 (8-bit) T1CN COMPARATOR
TIMER 1 INTERRUPT
INT 1 INTERRUPT
Figure 12-7 8-bit Capture Mode
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T0
up -c ou nt
n n-1
This value is loaded to CDR0
~ ~
~ ~
9 8 7 6
5 4 3 2 1 0
~ ~
TIME
Ext. INT0 Pin Interrupt Request (INT0IF)
Interrupt Interval Period
Ext. INT0 Pin Interrupt Request (INT0IF)
Capture (Timer Stop)
Delay Clear & Start
Figure 12-8 Input Capture Operation
Ext. INT0 Pin Interrupt Request (INT0IF)
Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H
Interrupt Request (T0IF)
FFH FFH
T0
13H 00H 00H
Figure 12-9 Excess Timer Overflow in Capture Mode
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12.4 16-bit Capture Mode
16-bit capture mode is the same as 8-bit capture, except that the Timer register is running with 16 bits. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0.
TM0
ADDRESS : 0E0H RESET VALUE : --000000B
In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively.
-
-
CAP0 1
T0CK2 X
T0CK1 X
T0CK0 X
T0CN X
T0ST X
TM1
POL X
16BIT 1
PWME 0
CAP1 X
T1CK1 1
T1CK0 1
T1CN X
T1ST X
ADDRESS : 0E2H RESET VALUE : 00000000B
X : The value "0" or "1" corresponding your operation.
T0CK[2:0] Edge Detector EC0
1
T0ST 0 : Stop 1 : Clear and Start CLEAR
XIN SXIN
2
0X 1X
SCMR[1:0] INT0
/2 /4 /8 / 32 / 128 / 512 / 1024
MUX T0CN
T0 + T1 (16-bit)
T0IF COMPARATOR
TIMER 0 INTERRUPT
CAPTURE
CDR1 (8-bit)
CDR0 (8-bit)
TDR1 (8-bit)
TDR0 (8-bit) INT0IF
INT 0 INTERRUPT
IESR[1:0]
Figure 12-10 16-bit Capture Mode
12.5 8-Bit (16-Bit) Compare OutPut Mode
The GMS81C5108 has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin (R31) as shown in Figure 12-3 and Figure 12-6. Thus, pulse out is generated by the timer match. These operation is implemented to pin, R31/PWM. In this mode, the bit PWMO of Port Mode Register (PMR) should be set to "1", and the bit PWME of Timer1 Mode Register (TM1) should be cleared to "0". In addition, 16-bit Compare output mode is available, also. This pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation.
Oscillation Frequency f COMP = -------------------------------------------------------------------------------------2 x Prescaler Value x ( TDR + 1 )
12.6 PWM Mode
The GMS81C5108 has one high speed PWM (Pulse Width Modulation) function which shared with Timer1. In PWM mode, the R31/PWM pin operates as a 10-bit resolution PWM output port. For this mode, the bit PWM of Port Mode Register (PMR) and the bit PWME of timer1 mode register (TM1) should be set to "1" respectively. The period of the PWM output is determined by the T1PPR (PWM Period Register) and PWMHR[3:2] (bit3,2 of PWM High Register) and the duty of the PWM output is determined by the T1PDR (PWM Duty Register) and PWMHR[1:0] (bit1,0 of PWM High Register). The user can use PWM data by writing the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWMHR[3:2]. And the duty value can be used with the T1PDR and the PWMHR[1:0] in the same way. The T1PDR is configured as a double buffering for glitch-
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less PWM output. In Figure 12-11, the duty data is transferred from the master to the slave when the period data matched to the counted value. (i.e. at the beginning of next duty cycle). The bit POL0 of TM1 decides the polarity of duty cycle. The duty value can be changed when the PWM outputs. However the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 12-13. As it were, the absolute duty time is not changed in varying frequency.
Note: If the user need to change mode from the Timer1 mode to the PWM mode, the Timer1 should be stopped firstly, and then set period and duty register value. If user writes register values and changes mode to PWM mode while Timer1 is in operation, the PWM data would be different from expected data in the beginning.
PWM Period = [PWMHR[3:2]T1PPR+1] X Source Clock PWM Duty = [PWMHR[1:0]T1PDR+1] X Source Clock
If it needed more higher frequency of PWM, it should be reduced resolution.
Note: If the duty value and the period value are same, the PWM output is determined by the bit POL0 (1: High, 0: Low). And if the duty value is set to "00H", the PWM output is determined by the bit POL0(1: Low, 0: High). The period value must be same or more than the duty value, and 00H cannot be used as the period value.
Frequency Resolution 10-bit 9-bit 8-bit 7-bit T1CK[1:0] =00 (250nS) 3.9KHz 7.8KHz 15.6KHz 31.25KHz T1CK[1:0] =01 (500nS) 1.95KHz 3.9KHz 7.8KHz 15.6KHz T1CK[1:0] =10 (2uS) 0.49KHZ 0.98KHZ 1.95KHz 3.90KHz
The relation of frequency and resolution is in inverse proportion. Table 12-2 shows the relation of PWM frequency vs. resolution.
Table 12-2 PWM Frequency vs. Resolution at 4MHz
TM1
POL X
16BIT 0
PWME 1
CAP1 0
T1CK1 X
T1CK0 X
T1CN X
T1ST X
ADDRESS : 0E2H RESET VALUE : 00H
PWMHR
-
-
-
-
PWM03 X
PWM02 X
PWM01 X
PWM00 X
ADDRESS : 0E5H RESET VALUE : ----0000B Bit Manipulation Not Available
Period High PWMHR[3:2]
Duty High
X : The value "0" or "1" corresponding your operation.
T1ST T0 clock source 0 : Stop 1 : Clear and Start
T1PPR (8-bit) COMPARATOR SQ
1
R31/PWM
CLEAR T1 (8-bit)
XIN SXIN
2
0X 1X
/1 /2 /8
MUX
R PWMO [PMR.6] POL
COMPARATOR T1CK[1:0] T1CN Slave T1PDR (8-bit)
SCMR[1:0]
PWMHR[1:0] Master
T1PDR (8-bit)
Figure 12-11 PWM Mode
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~ ~
~ ~
fxin
~~ ~~
~~~ ~~~
T1
00
01
02
03
04
7F
80
81
3FF
00
01
02
PWM POL=1 PWM POL=0
Duty Cycle [80H+1 x 250nS = 32.25uS] Period Cycle [3FFH x 250nS = 256uS, 3.9kHz] T1CK[1:0] = 00 (250nS) PWMHR = 0CH T1PPR = FFH T1PDR = 80H
Duty PWM01 0 PWM00 0 T1PDR (8-bit) 80H Period PWM03 1 PWM02 1 T1PPR (8-bit) FFH
Figure 12-12 Example of PWM at 4MHz
T 1C K [1:0] = 10 (2uS ) P W M H R = 00 H T 1P P R = 0D H T 1P D R = 04 H Source clock T1 PWM POL=1 Duty Cycle [04H+1 x 2uS = 10uS] Period Cycle [0DH+1 x 2uS = 28uS, 35.7kHz]
00 01 02 03 04 05 06 07 08
~ ~
Write T1PPR to 09H
~ ~
09 0A 0B 0C 0D 00 01 02 03 04 05 06 07 08 09 00 01 02 03
Duty Cycle [04H+1 x 2uS = 10uS]
Period Cycle [09H+1 x 2uS = 20uS, 50kHz]
Figure 12-13 Example of Changing the Period in Absolute Duty Cycle (@4MHz) Example: Timer1 @4Mhz, 4kHz - 20% duty PWM mode LDM LDM LDM LDM LDM LDM LDM R3DR,#0000_XX1XB TM1,#0010_0000B T1PWHR,#0000_1100B T1PPR,#1110_0111B T1PDR,#1100_0111B RSR,#X1XX_XXXXB TM1,#0010_0011B ;R31 output ;pwm enable ;20% duty ;period 250uS ;duty 50uS ;set pwm port. ;timer1 start
~ ~
Period changed
04
Duty Cycle [04H+1 x 2uS = 10uS]
X means don't care
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13. Watch Timer/Watch Dog Timer
This has two functions, one is the interrupt occurrence for watch time and the other is the signal generation of WDTOUTB for watch dog.
13.1 Watch Timer
The watch timer consists of the clock selector, 21-bit binary counter and watch timer mode register. It is a multi-purpose timer. It is generally used for watch design. The bit 1,2 of WTMR select the clock source of watch timer among sub-clock, fMAIN/27 of main-clock and fMAIN of main-clock. The fMAIN of main-clock is used usually for watch timer test, so generally it is not used for the clock source of watch timer. The fMAIN/27 of main-clock is used when the single clock system is organized. In fMAIN/27 clock source, if the CPU enters into stop mode, the mainclock is stopped and then watch timer is also stopped. If the sub-clock is the source clock, the watch timer count cannot be stopped. Therefore, the sub-clock does not stop but continues to oscillate even when the CPU is in the STOP mode. The timer counter consists of 21-bit binary counter and it can count to max 64 seconds at sub-clock. The bit 2, 3 of WTMR select the interrupt request interval of watch timer among 2Hz, 4Hz, 16Hz and 1/64Hz.
WTMR (Watch Timer Mode Register)
Bit : 7 R/W 6 WTEN R/W 5 WDTEN R/W 4 WDTCL R/W 3 WTIN1 R/W 2 WTIN0 R/W 1 WTCK1 R/W 0 WTCK0 ADDRESS: 0EFH INITIAL VALUE:-0000000B
WTEN (Watch Timer Enable Bit) 0: Watch Timer Disable 1: Watch Timer Enable WDTCL (Watch Dog Timer Clear Bit) 0: Timer running 1: WDT Clear (Auto reset after 1 cycle) WTCK[1:0] (Watch Timer Clock Source Selection) 00: Sub. Clock (fSUB) 01: Main Clock (fMAIN/27) 10: Main Clock (fMAIN) 11: -
WDTEN (Watch Dog Timer Enable Bit) 0: Watch Dog Timer Disable 1: Watch Dog Timer Enable WTIN[1:0] (Watch Timer Interrupt Interval Selection) 00: 16Hz 01: 4Hz 10: 2Hz 11: 1/64Hz
* When fSUB = 32.768 kHz and fMAIN = 4.19 MHz
Figure 13-1 Watch Timer Mode Register
WTCK[1:0] fSUB fMAIN/27 fMAIN 16 Hz 4 Hz 2 Hz 1/64 Hz
WTIN[1:0]
MUX
21 BIT Binary Counter
MUX
WTIF
Watch Timer Interrupt
WTEN 2 Bit F/F WDTCL WDTEN
WDTOUT
Figure 13-2 Watch Timer Block Diagram
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13.2 Watch Dog Timer
The watch dog timer (WDT) function is used for checking program malfunction. If the watch dog timer is not reset in a fixed time, the WDTOUTB pin outputs a low signal. Therefore, by connecting the WDTOUTB pin and the reset pin externally, the MCU can be reset when the malfunction is occurred. Usually the stop mode is used to reduce the power consumption. When the stop mode is released by watch timer interrupt, it is recommend to set the WDTCL to clear the 2-Bit counter and enter the stop mode. If the clock source is 1/64Hz, the WDTCL cannot be cleared in 500ms. In this case, the user should disable the WDT by clearing the WDTEN or disconnect the WDTOUTB pin and reset pin. Usage of Watch Timer in STOP Mode When the system is off and the watch should be kept working, follow the steps below. 1. Determines which mode is to be performed between main mode and sub mode when the MCU is released from Stop mode and set the clock source of watch timer to sub-clock. 2. Enters in STOP mode. 3. After released by watch timer interrupt, counts up timer and refreshes LCD Display. When the performing count up and refresh the LCD, the CPU operates either in main frequency mode or sub frequency mode. 4. Enters in STOP mode again. 5. Repeats 3 and 4. When using STOP mode, if the watch timer interrupt interval is selected to 2Hz, the power consumption can be reduced considerably.
fW/211 (16Hz)
fW/213 (4Hz)
fW/214 (2Hz)
INTWT (16Hz)
INTWT (4Hz)
INTWT (2Hz)
WDTCL WDT Reset Signal
WDTOUTB 500msec 500msec
The WDTCL should be set during this interval.
The WDTCL should be set during this interval.
If the WDTCL is not cleared during this interval, the WDTOUTB will be low during next interval.
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14. ANALOG TO DIGITAL CONVERTER
The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has four analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The analog supply voltage is connected to AVDD of ladder resistance of A/D module. The A/D module has two registers which are the A/D mode register (ADMR) and A/D data register (ADDR). The ADMR register, shown in Figure 14-1, controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. To use analog inputs, each port should be assigned analog input port by
ADAN[1:0] ANEN A/D Converter Data Register 11 ADDR (8-bit) ANEN ADDRESS : 0EDH RESET VALUE : Undefined
setting input mode by R2DR direction register. And select the corresponding channel to be converted by setting ADAN[1:0]. The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADDR contains the result of the A/D conversion. When the conversion is completed, the result is loaded into the ADDR, the A/D conversion status bit ADF is set to "1", and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 14-1. The A/D status bit ADF is automatically set when A/ D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 30 uS (at fMAIN = 4MHz).
R23/AN3
R22/AN2
ANEN
10
Sample & Hold S/H
Comparator Successive Approximation Circuit
A D IF
R21/AN1
ANEN
01
A/D Interrupt
R20/AN0
ANEN
00
Resistor Ladder Circuit
AVDD
ADMR (A/D Mode Register)
Bit : 7 R/W 6 ADEN 5 4 R/W 3 ADAN1 R/W 2 ADAN0 R/W 1 ADST R 0 ADF ADDRESS : 0ECH RESET VALUE : -0--0001B
ADEN (A/D Converter Enable bit) 1 : Enable 0 : Disable ADST (A/D Start bit) 1 : A/D Conversion is started After 1 cycle, cleared to "0" 0 : Bit force to zero ADF (A/D Status bit) 0 : A/D Conversion is in process 1 : A/D Conversion is completed
ADAN[1:0] (A/D Converter Input Selection) 00 : Channel 0 (R20/AN0) 01 : Channel 1 (R21/AN1) 10 : Channel 2 (R22/AN2) 11 : Channel 3 (R23/AN3)
ADDR (A/D Data Register)
Bit : R 7 ADD7 R 6 ADD6 R 5 ADD5 R 4 ADD4 R 3 ADD3 R 2 ADD2 R 1 ADD1 R 0 ADD0 ADDRESS : 0EDH RESET VALUE : Undefined
Figure 14-1 A/D Converter Block Diagram & Registers
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ENABLE A/D CONVERTER
to noise on pins AVDD and AN0 to AN3. Since the effect increases in proportion to the output impedance of the analog input source, it is recommended that a capacitor is connected externally as shown below in order to reduce noise.
A/D INPUT CHANNEL SELECT Analog Input ANALOG REFERENCE SELECT 100~1000pF AN0~AN3
A/D START (ADST = 1)
Figure 14-3 Analog Input Pin Connecting Capacitor
NOP
(3) Pins AN0/R20 to AN3/R23
NO ADF = 1 YES READ ADDR
The analog input pins AN0 to AN3 also function as input/ output port (PORT R2) pins. When A/D conversion is performed with any of pins AN0 to AN3 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. (4) AVDD pin input impedance A series resistor string of approximately 10K is connected between the AVDD pin and the VSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVDD pin and the VSS pin, and there will be a large reference voltage error.
Figure 14-2 A/D Converter Operation Flow
A/D Converter Cautions (1) Input range of AN0 to AN3 The input voltages of AN0 to AN3 should be within the specification range. In particular, if a voltage above AVDD or below VSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminated. The conversion values of the other channels may also be affected. (2) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid
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15. Buzzer Output Function
The buzzer driver consists of 6-bit binary counter, the buzzer data register BDR and the clock selector. It generates square-wave which is very wide range frequency (500 Hz~125 KHz at fMAIN = 4MHz) by user programmable counter. Pin R04 is assigned for output port of Buzzer driver by setting the bit BUZ of Port Mode Register (PMR) to "1". The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BDR. It is increased from 00H until it matches with BDR[5:0]. Also, it is cleared by counter overflow and count up to output the square wave pulse of duty 50%.
BDR (Buzzer Data Register)
Bit : W 7 BCK1 W 6 BCK0 W 5 BCD5 W 4 BCD4 W 3 BCD3 W 2 BCD2 W 1 BCD1 W 0 BCD0 ADDRESS : 0FDH RESET VALUE : 00H Bit manipulation is not available.
The bit 0 to 5 of BDR determines output frequency for buzzer driving. BCD is undefined after reset, so it must be initialized to between 0H and 3FH by software. Note that BDR is a write-only register. Frequency calculation is following as shown below.
Oscillator Frequency f BUZ ( Hz ) = -----------------------------------------------------------------------------2 x Prescaler Ratio x ( BCD + 1 )
The bits BCK1, BCK0 of BDR select the source clock from prescaler output
fBUZ: BUZ pin frequency Prescaler ratio: Prescaler divide ratio by BDR[7:6] BCD value: 6-bit compare data, BCD[5:0].
BCK[1:0] (Buzzer Clock Source) 00: fMAIN/23 01: fMAIN/24 10: fMAIN/25 11: fMAIN/26 or fSUB/23 or fSUB/24 or fSUB/25 or fSUB/26
BCD[5:0] (Buzzer Control Data) Buzzer Period Data
PMR (Port Mode Register)
PWMO
-
BUZ
EC0
INT2
INT1
INT0
ADDRESS :0D9H RESET VALUE : -0-00000B
BUZ (Buzzer Output) 0: R04 Port (turn off buzzer) 1: BUZ port (turn on buzzer) SCMR[1:0]
2
XIN SXIN
0X 1X
/8 / 16 / 32 / 64
MUX
COUNTER (6-bit)
F/F BCK[1:0] COMPARATOR BCD (6-bit) BUZ [PMR.4] R04/BUZ PIN
Figure 15-1 Buzzer Driver Example: 2.5kHz output at 4MHz. LDM LDM LDM
X means don't care
R0DR,#XXX1_XXXXB BDR,#1001_1000B PMR,#XXX1_XXXXB
;Buzzer ON
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Buzzer Output Frequency When main-frequency is 4MHz, buzzer frequency is shown as below and if sub-frequency is selected as clock
BDR [5:0] 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Frequency Output (kHz) 00 250.000 125.000 83.333 62.500 50.000 41.667 35.714 31.250 27.778 25.000 22.727 20.833 19.231 17.857 16.667 15.625 14.706 13.889 13.158 12.500 11.905 11.364 10.870 10.417 10.000 9.615 9.259 8.929 8.621 8.333 8.065 7.813 01 125.000 62.500 41.667 31.250 25.000 20.833 17.857 15.625 13.889 12.500 11.364 10.417 9.615 8.929 8.333 7.813 7.353 6.944 6.579 6.250 5.952 5.682 5.435 5.208 5.000 4.808 4.630 4.464 4.310 4.167 4.032 3.906 10 62.500 31.250 20.833 15.625 12.500 10.417 8.929 7.813 6.944 6.250 5.682 5.208 4.808 4.464 4.167 3.906 3.676 3.472 3.289 3.125 2.976 2.841 2.717 2.604 2.500 2.404 2.315 2.232 2.155 2.083 2.016 1.953 11 31.250 15.625 10.417 7.813 6.250 5.208 4.464 3.906 3.472 3.125 2.841 2.604 2.404 2.232 2.083 1.953 1.838 1.736 1.645 1.563 1.488 1.420 1.359 1.302 1.250 1.202 1.157 1.116 1.078 1.042 1.008 0.977
source, buzzer frequency is used after dividing by 128.
BDR [5:0] 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
Frequency Output (kHz) 00 7.576 7.353 7.143 6.944 6.757 6.579 6.410 6.250 6.098 5.952 5.814 5.682 5.556 5.435 5.319 5.208 5.102 5.000 4.902 4.808 4.717 4.630 4.545 4.464 4.386 4.310 4.237 4.167 4.098 4.032 3.968 3.906 01 3.788 3.676 3.571 3.472 3.378 3.289 3.205 3.125 3.049 2.976 2.907 2.841 2.778 2.717 2.660 2.604 2.551 2.500 2.451 2.404 2.358 2.315 2.273 2.232 2.193 2.155 2.119 2.083 2.049 2.016 1.984 1.953 10 1.894 1.838 1.786 1.736 1.689 1.645 1.603 1.563 1.524 1.488 1.453 1.420 1.389 1.359 1.330 1.302 1.276 1.250 1.225 1.202 1.179 1.157 1.136 1.116 1.096 1.078 1.059 1.042 1.025 1.008 0.992 0.977 11 0.947 0.919 0.893 0.868 0.845 0.822 0.801 0.781 0.762 0.744 0.727 0.710 0.694 0.679 0.665 0.651 0.638 0.625 0.613 0.601 0.590 0.579 0.568 0.558 0.548 0.539 0.530 0.521 0.512 0.504 0.496 0.488
Table 15-1 Buzzer Output Frequency
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16. Serial Communication Interface
The SCI module allows 8-bits of data to be synchronously transmitted and received. This is useful for communication with other peripheral of microcontroller devices.This conSIOM (Seriol I/O Mode Register)
Bit : R/W 7 POL R/W 6 MSBS R/W 5 SIO1 R/W 4 SIO0 R/W 3 SICK1 R/W 2 SICK0 R/W 1 SIOST R/W 0 SIOSF ADDRESS : 0FEH RESET VALUE : 00000001B
sists of serial I/O data register, serial I/O mode register, clock selection circuit octal counter and control circuit as shown in Figure 16-1.
POL (Polarity Selection) 0 : Data Transmission at falling edge (Received data latch at rising edge) 1 : Data Transmission at rising edge (Received data latch at falling edge) SIO[1:0] (Serial I/O Operation Mode) 00 : Normal Port (R05, R06, R07) 01 : Transmit Mode (SCK, SO, R07) 10 : Receive Mode (SCK, R06, SI) 11 : Transmit & Receive Mode (SCK, SO, SI) SIOST (Serial I/O Operation Start Control) 0 : SIO Operation Stop 1 : SIO Operation Start (After one SCK clock become "0")
MSBS (MSB First Transmit and Receive Selection) 0 : LSB First 1 : MSB First SICK[1:0] (Serial I/O Clock Source Selection) 00: fMAIN /4 or fSUB /4 01: fMAIN /16 or fSUB /16 10: T0O (Timer 0 Output) 11: External Clock SIOSF (Serial I/O Status Flag) 0 : During SIO Operation 1 : SIO Operation Finished
SIOD (Serial I/O Data Register)
Bit : R/W 7 SIOD7 R/W 6 SIOD6 R/W 5 SIOD5 R/W 4 SIOD4 R/W 3 SIOD3 R/W 2 SIOD2 R/W 1 SIOD1 R/W 0 SIOD0 ADDRESS : 0FFH RESET VALUE : Undefined
SCMR[1:0]
2
SICK[1:0]
2
XIN SXIN
0X 1X
fMAIN/22 or fSUB/22 Prescaler fMAIN/24 or fSUB/24
00 01 10 11
POL
SIOST
Start Complete
SIOSF
Clear
SIO Control Circuit
T0OV(Timer 0 Overflow) R05SCK SIO[1:0] = 00
1
Clock
Shift Clock
Octal Counter (3-Bit) SCK SICK[1:0] 11 & SIO[1:0] 00 MSB
0
SIO Interrupt SIOIF
MSBS LSB 0 R06/SO
R07/SI
1
SIOD(8-Bit) SIO Data Register
SIO[1] = 1 MSBS
1
SIO[0] = 1
Figure 16-1 SCI Registers and Block Diagram
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To accomplish communication, typically three pins are used: - Serial Data In - Serial Data Out - Serial Clock R07/SI R06/SO R05/SCK
ting the SIO1 and SIO0 and the transfer clock rate is decided by setting the SICK1 and SICK0 of SCI Mode Control Register as shown in Figure 16-1. And the polarity of transfer clock is selected by setting the POL. The MSBS bit is used to select which bit would be sending or receiving.
The serial data transfer operation mode is decided by setPort Selection R05/SCK R05 SCK SCK SCK R06/SO R06 SO R06 SO R07/SI R07 R07 SI SI
SIO1 0 0 1 1
SIO0 0 1 0 1
Function Selection Transmit Mode Receive Mode Transmit and Receive
16.1 Data Transmit/Receive Timing
The SCI operation is executed by setting the SIOST bit to "1". The SIOST bit is cleared to "0" automatically after 1 machine cycle. The Serial output data is shift in or shift out
MSBS=0 SIOST R05/SCK (POL=1) R05/SCK (POL=0) R06/SO R07/SI SIOSF SIOIF (SCI Int. Req)
D0 D1 D2 D3 D4 D5 D6 D7
at edge decided by POL. Interrupt is occurred when the eight in/out datas is counted by octal counter.
D0
D1
D2
D3
D4
D5
D6
D7
Figure 16-2 SCI Timing Diagram
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16.2 The method of Serial I/O
1. Select transmission/receiving mode When external clock is used, the frequency should be less than 1MHz and recommended duty is 50%. 2. In case of sending mode, write data to be send to SIOD. 3. Set SIOST to "1" to start serial transmission. If both transmission mode is selected and transmission is performed simultaneously it would be made error. 4. The SIO interrupt is generated at the completion of SIO and SIOSF is set to "1". 5. In case of receiving mode, the received data is acquired by reading the SIOD.
SIOST SCLK [R05] (POL=1)
SOUT [R06] SIN [R07]
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
SIOSF
SIOIF
Figure 16-3 SCI Timing Diagram at POL=1
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17. INTERRUPTS
The GMS81C5108 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flag (IRQH, IRQL), Interrupt Edge Selection Register (IESR), priority circuit and Master enable flag ("I" flag of PSW). The configuration of interrupt circuit is shown in Figure 17-1 and Interrupt priority is shown in Table 17-1 . The flags that actually generate these interrupts are bit INT0F, INT1F and INT2F in Register IRQH. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 and Timer 2 Interrupts are generated by T0IF and T1IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The Basic Interval Timer Interrupt is generatInternal bus line
ed by BITIF which is set by overflow of the Basic Interval Timer Register (BITR).
Reset/Interrupt Symbol Priority 1 2 3 4 5 6 7 8 9 10 11 Vector Addr. FFFEH FFFCH FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H
Hardware Reset RESET Key Scan Interrupt KS BIT Interrupt BIT External Interrupt 0 INT0 External Interrupt 1 INT1 Timer 0 Interrupt T0 Timer 1 Interrupt T1 External Interrupt 2 INT2 Remocon Interrupt REM AD Interrupt AD SIO Interrupt SIO Watch Timer Interrupt WT
Table 17-1 Interrupt Priority
IRQH Key Scan BIT Ext. Int. 0 Ext. Int. 1
IESR KSIF BITIF INT0IF INT1IF
IENH 6 5 4 3
Interrupt Enable Register (Higher byte)
I-flag is in PSW, it is cleared by "DI", set by "EI" instruction.When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware.
Release STOP
Timer 1 Ext. Int. 2
T1IF INT2IF
1 0
Priority Control
Timer 0
TOIF
2
To CPU I Flag Interrupt Master Enable Flag Interrupt Vector Address Generator
Remocon A/D Converter SIO WT
REMIF ADIF SIOIF WTIF
6 5 4 3
IRQL
IENL
Interrupt Enable Register (Lower byte)
Internal bus line
Figure 17-1 Block Diagram of Interrupt Function
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The External Interrupts INT0, INT1 and INT2 can each be transition-activated (1-to-0, 0-to-1 and both transiton).The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flag (IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 17-2. These registers are composed of interrupt enable flags of each interrupt source, these flags determine whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW
IENH (Interrupt Enable High Register)
Bit : 7 R/W 6 KSE R/W 5 BITE R/W 4 INT0E R/W 3 INT1E
contains also a master enable bit, I-flag, which disables all interrupts at once. When an interrupt is occurred, the I-flag is cleared and disable any further interrupt, the return address and PSW are pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits. The interrupt request flag bit(s) must be cleared by software before re-enabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and written.
R/W 2 T0E
R/W 1 T1E
R/W 0 INT2E ADDRESS : 0DBH RESET VALUE : -0000000B
IENL (Interrupt Enable Low Register)
Bit : 7 R/W 6 REME R/W 5 ADE R/W 4 SIOE R/W 3 WTE 2 1 0 ADDRESS : 0DAH RESET VALUE : -0000---B
Enables or disables the interrupt individually If flag is cleared, the interrupt is disabled. 0 : Disable 1 : Enable
IRQH (Interrupt Request High Register)
Bit : 7 R/W 6 KSIF R/W 5 BITIF R/W 4 INT0IF R/W 3 INT1IF R/W 2 T0IF R/W 1 T1IF R/W 0 INT2IF ADDRESS : 0DDH RESET VALUE : -0000000B
IRQL (Interrupt Request Low Register)
Bit : 7 R/W 6 REMIF R/W 5 ADIF R/W 4 SIOIF R/W 3 WTIF 2 1 0 ADDRESS : 0DCH RESET VALUE : -0000---B
Shows the interrupt occurrence 0 : Not occurred 1 : Interrupt request is occurred
Figure 17-2 Interrupt Enable Registers and Interrupt Request Registers
17.1 Interrupt Sequence
An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 f OSC (2 s at fMAIN=4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed.
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System clock
Instruction Fetch Address Bus
PC SP SP-1 SP-2 V.L. V.H. New PC
Data Bus Internal Read Internal Write
Not used
PCH
PCL
PSW
V.L.
ADL
ADH
OP code
Interrupt Processing Step
Interrupt Service Routine
V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents.
Figure 17-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction
Basic Interval Timer Vector Table Address
Entry Address
The following method is used to save/restore the generalpurpose registers. Example: Register saving
0FFFAH 0FFFBH
012H 0E3H
0E312H 0E313H
0EH 2EH
INTxx:
PUSH PUSH PUSH
A X Y
;SAVE ACC. ;SAVE X REG. ;SAVE Y REG.
Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program.
interrupt processing
An interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. Saving/Restoring General-purpose Register During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. If necessary, these registers should be saved by the software. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers.
POP POP POP RETI
Y X A
;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN
General-purpose registers are saved or restored by using push and pop instructions.
main routine acceptance of interrupt
interrupt service routine saving registers
restoring registers interrupt return
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17.2 BRK Interrupt
Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 17-4.
B-FLAG BRK or TCALL0 =1 BRK INTERRUPT ROUTINE RETI
=0
TCALL0 ROUTINE
RET
Figure 17-4 Execution of BRK/TCALL0
17.3 Multi Interrupt
If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. .
Main Program service
TIMER 1 service INT0 service
enable INT0 disable other EI
Occur TIMER1 interrupt
Occur INT0
Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend.
TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI A X Y IENH,#80H IENL,#0
enable INT0 enable other
;Enable INT0 only ;Disable other ;Enable Interrupt
In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine.
IENH,#0FFH ;Enable all interrupts IENL,#0F0H Y X A
Figure 17-5 Execution of Multi Interrupt
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17.4 External Interrupt
The external interrupt on INT0, INT1 and INT2 pins are edge triggered depending on the edge selection register IESR (address 0D8H) as shown in Figure 17-6. The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. Example: To use as an INT0 and INT2
: : ;**** Set port as an input port R0 LDM R0DR,#1111_1010B ; ;**** Set port as an interrupt port LDM PMR,#0000_0101B ; ;**** Set Falling-edge Detection LDM IESR,#0001_0001B : : :
INT0
INT0IF
INT0 INTERRUPT
edge selection
INT1
INT1IF
INT1 INTERRUPT
Response Time The INT0, INT1 and INT2 edge are latched into INT0F, INT1F and INT2F at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a maximum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. Interrupt response timings are shown in Figure 17-7.
INT2
INT2IF
INT2 INTERRUPT
IESR [0D8H]
IESR (Ext. Interrupt Edge Selection Register) Interrupt Edge Selection Register)
Bit : 7 6 R/W 5 INT21 R/W 4 INT20 R/W 3 INT11 R/W 2 INT10 R/W 1 INT01 R/W 0 INT00
INT2[1:0] (INT2 Edge Selections) 00 : Int. Disable 01 : Falling (1-to-0 transition) 10 : Rising (0-to-1 transition) 11 : Both (Rising & Falling) INT1[1:0] (INT1 Edge Selection) 00 : Int. Disable 01 : Falling (1-to-0 transition) 10 : Rising (0-to-1 transition) 11 : Both (Rising & Falling)
ADDRESS : 0D8H RESET VALUE : --000000B
INT0[1:0] (INT0 Edge Selections) 00 : Int. Disable 01 : Falling (1-to-0 transition) 10 : Rising (0-to-1 transition) 11 : Both (Rising & Falling)
Figure 17-6 External Interrupt Block Diagram
max. 12 fOSC
8 fOSC
Interrupt Interrupt latched goes active
Interrupt processing
Interrupt routine
Figure 17-7 Interrupt Response Timing Diagram
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18. KEY SCAN
The key-scan block consists of key scan mode register (KSMR) and R1 pull-up register (R1PU). When the key scan interrupt is used, key scan mode register KSMR (address 0F0H) should be set properly as shown in Figure 181. The pins which is to be used as key scan input should be set by KSMR and the strobe output pins should be set as open drain. The strobe output pins could be selected from among R0[7:0], R1[7:0], R2[3:0] and R3[3:0]. If the "L" signal is input to any one or more of key scan input pins, the KSIF request flag is set to "1". This generates an interrupt request. It also can be used in the way of release from STOP mode.
VDD
R1PU[7:0]
KSMR
R10/KS0 R11/KS1 R12/KS2 R13/KS3 R14/KS4 R15/KS5 R16/KS6 R17/KS7
Key Scan Interrupt KSIF
KSMR (Key Scan Mode Register)
Bit : R/W 7 KS7 R/W 6 KS6 R/W 5 KS5 R/W 4 KS4 R/W 3 KS3 R/W 2 KS2 R/W 1 KS1 R/W 0 KS0 ADDRESS : 0F0H RESET VALUE : 00H
0 : Port Function (I/O) Selection 1 : Key Scan Input Selection
Figure 18-1 Key Scan Interrupt Block Diagram
Usage of Key Scan When key board scanning, it is recommended that set the output strobe to "L" first and then read R1 port after 60us
;Program Example, LDM CALL LDA R3,#0000_1110b ;R3<0> Port set to low Delay_60us ;60us time delay routine R1 ;read R1 port 60s R3<0>
delay time. Because the rising time of the output strobe port from "L" to "H" is so long. The Figure 18-2 explain this reason.
If the rising time is so long, the key scanning could be detected double key with R3<0> and R3<1>.
60s R3<1> R1 Port Read Timing
Figure 18-2 Key Scan Timing
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19. LCD DRIVER
The GMS81C5108 has the circuit that directly drives the liquid crystal display (LCD) and its control circuit. The Segment/Common Driver directly drives the LCD panel, and the LCD Controller generates the segment/common signals according to the RAM which stores display data. In addition, VCL2 ~ VCL0 pin are provided as the drive power pins. The GMS81C5108 has the following pins connected with LCD. 1. Segment output port 37 pins (SEG0-SEG36) 2.Common output port 4 pins (COM0-COM3)
19.1 Configuration of LCD driver
Figure 19-1 shows the configuration of the LCD driver.
SEG0
Display Data Select Control
Display Memory (37Nibbles)
Display Data Buffer register
INTERNAL BUS LINE
WTMR[1:0]
00 01 10
fSUB fMAIN/27 fMAIN
MUX LCD Timing Control / 32 Prescaler / 64 / 128 / 256 Select clock SEG35/COM2 LCD Control Register LCR[0F1H] LCDEN Select Duty COM0 SEG36/COM1 MUX clock
Segment/Common Driver
SEG33 SEG34/COM3
Figure 19-1 LCD Driver Block Diagram
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19.2 Control of LCD Driver Circuit
The LCD driver is controlled by the LCD Control Register (LCR). The LCR[1:0] determines the frequency of COM signal scanning of each segment output. RESET clears the LCD control register LCR values to logic zero. The LCD display can continue to operate during SLEEP and STOP modes if a sub-frequency clock is used as system clock source. The constant voltage booster circuit for using LCD driver is built in, so the definite voltage could supplied regardless of power source voltage fluctuations.
LCR(LCD Control Register)
Bit : 7 6 R/W 5 LCDEN R/W 4 VBCL R/W 3 LCDD1 R/W 2 LCDD0 R/W 1 LCK1 R/W 0 LCK0 ADDRESS : 0F1H RESET VALUE : --000000B
Note: The Sub clock is used as voltage booster source clock, so the stabilization time is need to use voltage booster. Normally, the stabilization time is need more than 500ms. The external bias registers cannot be used for LCD display supply voltage.
LCDEN (LCD Display Enable Bit) 0: LCD Display Disable 1: LCD Display Enable LCDD[1:0] (LCD Duty Selection) 00: 1/4 Duty 01: 1/3 Duty (COM[3] are used as SEG[34]) 10: 1/2 Duty (COM[3:2] are used as SEG[34:35]) 11: Static (COM[3:1] are used as SEG[34:36])
VBCL (Voltage Booster Enable Bit) 0: Voltage Booster Disable 1: Voltage Booster Enable LCK (LCD Clock source selection) 00: fS / 32 01: fS / 64 10: fS / 128 11: fS / 256
*The fs can be selected among fSUB (Sub clock), fMAIN/27 (Main clck) and fMAIN (Main clock). And sub or main is selected by WTCK[1:0] of WTMR.
Figure 19-2 LCD Control Register
Selecting Frame Frequency Frame frequency is set to the base frequency as shown in the following Table 19-1. The fS is selected to fSUB (sub clock) which is 32.768kHz.
Frame Frequency (Hz) LCR[1:0] 00 01 10 11 LCD clock Duty = Static fS / 32 fS / 64 fS / 128 fS / 256 1024 512 256 128 Duty = 1/2 512 256 128 64 Duty = 1/3 341.3 170.7 85.3 42.7 Duty = 1/4 256 128 64 32
Table 19-1 Setting of LCD Frame Frequency
The matters to be attended to use LCD driver In reset state, LCD source clock is sub clock. So, when the power is supplied, the LCD display would be flickered before the oscillation of sub clock is stabilized. It is recommended to use LCD display on after the stabilization time of sub clock is considered enough. If the LCD is reset during display, the display would be blotted by the capacity of LCD power circuit. The external circuit of constant voltage booster for using LCD driver is shown at right.
VCL2 VCL1 VCL0 C1~C4=0.47uF R1=400K R2=1M R1 C1 R2 C2 C3
GMS81C5108 GMS87C5108
CAPH C4 CAPL
Figure 19-3 LCD Power Booster Circuit
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19.3 LCD Display Memory
Display data are stored to the display data area (page 1) in the data memory. The display data stored to the display data area (address 0100H-0124H) are read automatically and sent to the LCD driver by the hardware. The LCD driver generates the segment signals and common signals in accordance with the display data and drive method. Therefore, display patterns can be changed by only overwriting the contents of the display data area with a program. The table look up instruction is mainly used for this overwriting. Figure 19.3 shows the correspondence between the display data area and the SEG/COM pins. The LCD lights when the display data is "1" and turn off when "0". LCD display memory in this location that are not used for LCD display can be allocated for general purpose use. The SEG data for display is controlled by RPR (RAM Paging Register).
Bit SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20
0
1
2
3
4
5
6
7 0124H 0123H 0122H 0121H 0120H 011FH 011EH 011DH 011CH 011BH 011AH 0119H 0118H 0117H 0116H 0115H 0114H 0113H 0112H 0111H 0110H 010FH 010EH 010DH 010CH 010BH 010AH 0109H 0108H 0107H 0106H 0105H 0104H 0103H 0102H 0101H 0100H
RPR (RAM Paging Register)
Bit : 7 6 5 4 R/W 3 R/W 2 R/W 1 RPR1 R/W 0 RPR0
SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13
ADDRESS : 0F3H RESET VALUE : ------00B
RAM Page Instruction 0 Page 0 Page 1 Page CLRG SETG SETG RPR1 x 0 0 RPR0 x 0 1
SEG12 SEG11 SEG10 SEG9 SEG8 SEG7
Figure 19-4 Setting of RAM Paging Register
SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0
COM0
COM1
COM2
Figure 19-5 LCD Display Memory
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19.4 Control Method of LCD Driver
Initial Setting Flow chart of initial setting is shown in Figure 19-6. Example: Driving of LCD
Select Frame Frequency
LDM : LDM SETG
LCR,#12H RPR,#1 #0 #0 {X}+ #025H C_LCD1 LCR.5
;fF=64Hz, 1/4 duty(fSUB= 32.768kHz) ;Select LCD Memory(1 page)
Clear LCD Display Memory
LDX C_LCD1: LDA STA CMPX BNE CLRG : SET1 :
;RAM Clear ;(0100H->0124H)
Turn on LCD
;Enable display
.
COM0 COM1 Setting of LCD drive method SEG0 Initialize of display memory SEG1 Example: display "2"
bit 7 6 5 4 3 2 1 0
COM2 COM3
Enable display
100H 101H
* *
* *
* *
* *
0 1
0 1
1 1
1 0
Note: * are don't care.
Figure 19-6 Initial Setting of LCD Driver
Figure 19-7 Example of Connection COM & SEG
Display Data Normally, display data are kept permanently in the program memory and then stored at the display data area by the table look-up instruction. This can be explained using character display with 1/4 duty LCD as an example as well as any LCD panel. The COM and SEG connections to the LCD and display data are the same as those shown is Figure 19-7. Following is showing the Programming example for displaying character.
Note: When power on RESET, sub oscillation start up time is required. Enable LCD display after sub oscillation is stabilized, or LCD may occur flicker at power on time shortly.
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: CLRG LDX GOLCD: Write into the LCD Memory LDA TAY LDA LDM SETG LDX STA XCN STA CLRG : DB DB DB DB DB DB DB DB DB DB
#;Address included the data ;to be displayed. ;LOAD FONT DATA ;Set RPR = 1 to access LCD ;Set Page 1 ;LOWER 4 BITS OF ACC. seg0 ;UPPER 4 BITS OF ACC. seg1 ;Set Page = 0 ; ; ; ; ; ; ; ; ; ; "0" "1" "2" "3" "4" "5" "6" "7" "8" "9"
FONT Font data
1101_0111B 0000_0110B 1110_0011B 1010_0111B 0011_0110B 1011_0101B 1111_0101B 0000_0111B 1111_0111B 0011_0111B
LCD Waveform The LCD duty can be selected by LCR register. The kinds of LCD waveforms are four totally. Among them, static and 1/4 duty waveforms are shown Figure 19-8.
1/4 Duty, 1/3 Bias Drive
COM0 COM1 COM2 COM3
COM0
VCL2 VCL1 VCL0 GND VCL2 VCL1 VCL0 GND VCL2 VCL1 VCL0 GND VCL2 VCL1 VCL0 GND VCL2 VCL1 VCL0 GND VCL2 VCL1 VCL0 GND VCL2 VCL1 VCL0 0 -VCL0 -VCL1 -VCL2 VCL2 VCL1 VCL0 0 -VCL0 -VCL1 -VCL2
COM1
SEG0 SEG1 COM2
COM0 COM1 COM2 SEG0 SEG1
SEG1 COM3
COM3
SEG0
SEG0 - COM0
SEG1 - COM0
Figure 19-8 Example of LCD drive output
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20. REMOCON CARRIER GENERATOR
The GMS81C5108 has a circuit to generate carriers for the remote controller. This circuit consists of Remocon Mode Register (RMR), Carrier Frequency High Selection (CFHS), Carrier Frequency Low Selection (CFLS), Remocon Data High Register (RDHR), Remocon Data Low Register (RDLR), Remocon Data Counter (RDC), Remocon Output Data Register (RODR) and Remocon Output Buffer (ROB) as shown in Figure 20-1. A carrier duty and frequency are determined by the contents of these registers. A source clock input to the 6-bit counter is selected by diving the frequency of the system clock by two (main or sub clock).
20.1 Remocon Signal Output Control
The output of the REMOUT pin which outputs carriers is controlled by RODR and ROB register. While the Bit-0 of RODR is "1", the REMOUT pin outputs a carrier signal generated by the remote controller carrier generator. While this Bit is "0", the output of the REMOUT pin is low. The content of the ROB is automatically transferred to the
REN 0 RDCK[2:0]
RODR by an interrupt signal generated by the 8-Bit timer. The content of the RODR.0 is output to the REMOUT pin. Namely, the REMOUT pin outputs a high-level signal when RODR.0 is "1" and a low-level signal when RODR.0 is "0".
fxin is fMAIN or fSUB.
SCMR[1:0]
2
XIN SXIN
0X 1X
Prescaler
/8 fxin / 16 fxin / 32 fxin / 64 fxin / 128 fxin / 256 fxin / 512
fxin
2
RDHR (8-Bit) RDLR (8-Bit) Comparator REMF MUX RDC(8Bit) RDPE REN Remocon Interrupt
ROB (1Bit)
/1 /2 fxin / 4 fxin / 8
fxin fxin
MUX
6-Bit Counter RODR (1Bit) Comparator REMOUT
REN 0 & CCK[1:0]
CFHS (6-Bit) CFLS (6-Bit)
RMR (Remocon Mode Register)
Bit : 7 R/W 6 REN R/W 5 CCK1 R/W 4 CCK0 R/W 3 RDPE R/W 2 RDCK2 R/W 1 RDCK1 R/W 0 RDCK0 ADDRESS : 0F6H RESET VALUE : -0000000B
REN (Remocon Operation Enable) 0 : Disable 1 : Enable RDCK[2:0] (Remocon Data Clock Selection) 000: fMAIN/23 or fSUB/23 001: fMAIN/24 or fSUB/24 010: fMAIN/25 or fSUB/25 011: fMAIN/26 or fSUB/26 100: fMAIN/27 or fSUB/27 101: fMAIN/28 or fSUB/28 110: fMAIN/29 or fSUB/29 111: Carrier Signal
RDPE (Remocon Data Pulse Enable) 0 : Disable 1 : Enable CCK[1:0] (Carrier Clock Source Selection) or fSUB 00: fMAIN 01: fMAIN/2 or fSUB/2 10: fMAIN/22 or fSUB/22 11: fMAIN/23 or fSUB/23
fMAIN: main-clock frequency fSUB: sub-clock frequency
Figure 20-1 Remocon Carrier Generator Block Diagram
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CFHS (Carrier Frequency High Selection)
Bit : 7 6 W 5 CFH5 W 4 CFH4 W 3 CFH3 W 2 CFH2 W 1 CFH1 W 0 CFH0 ADDRESS : 0F7H RESET VALUE : --111111B
Carrier High Interval = The Value of CFHS x Clock Source Period
CFLS (Carrier Frequency Low Selection)
Bit : 7 6 W 5 CFL5 W 4 CFL4 W 3 CFL3 W 2 CFL2 W 1 CFL1 W 0 CFL0 ADDRESS : 0F8H RESET VALUE : --111111B
Carrier Low Interval = The Value of CFLS x Clock Source Period
RDHR (Remocon Data High Register)
Bit : W 7 RDH7 W 6 RDH6 W 5 RDH5 W 4 RDH4 W 3 RDH3 W 2 RDH2 W 1 RDH1 W 0 RDH0 ADDRESS : 0F9H RESET VALUE : 11111111B
Remocon Data High Interval = The Value of RDHR x Clock Source Period
RDLR (Remocon Data Low Register)
Bit : W 7 RDL7 W 6 RDL6 W 5 RDL5 W 4 RDL4 W 3 RDL3 W 2 RDL2 W 1 RDL1 W 0 RDL0 ADDRESS : 00FAH RESET VALUE : 11111111B
Remocon Data Low Interval = The Value of RDLR x Clock Source Period
RDC (Remocon Data Counter)
Bit : R 7 RDC7 R 6 RDC6 R 5 RDC5 R 4 RDC4 R 3 RDC3 R 2 RDC2 R 1 RDC1 R 0 RDC0 ADDRESS : 00FAH RESET VALUE : 00000000B
Remocon Data Counter Value
RODR (Remocon Output Data Register)
Bit : 7 6 5 4 3 2 1 -
R/W 0 RDD0 ADDRESS : 0FBH RESET VALUE : -------0B
Remocon Data Output Value
ROB (Remocon Output Buffer)
Bit : 7 6 5 4 3 2 1 -
R/W 0 RDB0 ADDRESS : 0FCH RESET VALUE : -------0B
Remocon Data Output Buffer
Figure 20-2 Remocon Registers
20.2 Carrier Frequency
The carrier frequency and the pulse of data are calculated by below formula. The the lengths of carrier frequency and pulse of data are shown in Figure 20-3. tH = source clock(RMR[5:4]) x CFHS tL = source clock(RMR[5:4]) x CFHS fC (Carrier Frequency) = 1/(tH+tL) tDH = source clock(RMR[2:0]) x RDHR tDL = source clock(RMR[2:0]) x RDLR
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tH Carrier Frequency
tL
tDH Pulse of Data
ROD0 = 01H
tDL
ROD0 = 00H
As soon as the carrier interrupt is occurred, the content of ROB is transferred to RODR.
Figure 20-3 Carrier Frequency & Pulse of Data
The Table 20-1 shows high and low length of carrier frequency according to CFLS and CFHS. This only shows
Set Value CFHS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH CFLS 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH Selection of PS0 tH(us) 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75 7.00 7.25 7.50 7.75 tL(us) 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 5.25 5.50 5.75 6.00 6.25 6.50 6.75 7.00 7.25 7.50 7.75 Selection of PS2 tH(us) 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00 19.00 20.00 21.00 22.00 23.00 24.00 25.00 26.00 27.00 28.00 29.00 30.00 31.00 tL(us) 1.00 2.00 3.00 4.00 5.00 6.00 7.00 8.00 9.00 10.00 11.00 12.00 13.00 14.00 15.00 16.00 17.00 18.00 19.00 20.00 21.00 22.00 23.00 24.00 25.00 26.00 27.00 28.00 29.00 30.00 31.00
when the source clock is selected fMAIN and fMAIN/22 at 4MHz.
Set Value CFHS 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH CFLS 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH Selection of PS0 tH(us) 8.00 8.25 8.50 8.75 9.00 9.25 9.50 9.75 10.00 10.25 10.50 10.75 11.00 11.25 11.50 11.75 12.00 12.25 12.50 12.75 13.00 13.25 13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 tL(us) 8.00 8.25 8.50 8.75 9.00 9.25 9.50 9.75 10.00 10.25 10.50 10.75 11.00 11.25 11.50 11.75 12.00 12.25 12.50 12.75 13.00 13.25 13.50 13.75 14.00 14.25 14.50 14.75 15.00 15.25 15.50 15.75 Selection of PS2 tH(us) 32.00 33.00 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 42.00 43.00 44.00 45.00 46.00 47.00 48.00 49.00 50.00 51.00 52.00 53.00 54.00 55.00 56.00 57.00 58.00 59.00 60.00 61.00 62.00 63.00 tL(us) 32.00 33.00 34.00 35.00 36.00 37.00 38.00 39.00 40.00 41.00 42.00 43.00 44.00 45.00 46.00 47.00 48.00 49.00 50.00 51.00 52.00 53.00 54.00 55.00 56.00 57.00 58.00 59.00 60.00 61.00 62.00 63.00
Table 20-1 Length of Carrier Frequency (at 4MHz)
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Example:
Carrier Frequency = 37.8kHz, high = 8.52ms, low = 4.24ms, @4MHz Rem_sig: LDM LDM LDM CLR1 LDM LDM LDM LDX CALL SET1 SET1 SET1 Loop1: NOP CMPX BNE RMR,#0001_0010B CFHS,#18 CFLS,#35 ROD0 R_bit,#1111_1000B RDHR,#213 RDLR,#177 #9 DATA RMR.6 RMR.3 IENL.6 #0 Loop1 ROD0 ROB0 ;carrier clock(PS1), remocon data clock(PS5) ;carrier low(IR LED)=18*PS1(0.5us)=9us ;carrier high(IR LED)=35*PS1(0.5us)=17.5us ;213*5*PS5(8us)=8.52ms ;177*3*PS5(8us)=4.248ms
;Remocon operation enable ;Remocon data pulse enable ;Remocon int.
Finish: CLR1 CLR1 RET ;******** Data: ROL BCS CLR1 RET
R_bit Set_rob0 ROB0
Set_rob0:SET1ROB0 RET ;***********************************************; ; Remocon int service routine ; ;***********************************************; ; Remocon_INT: CALL DEC RETI Data X
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21. OSCILLATOR CIRCUIT
The GMS81C5108 has two oscillation circuits internally. XIN and XOUT are input and output for main frequency and SXIN and SXOUT are input and output for sub frequency,
C1 XOUT
respectively, inverting amplifier which can be configured for being used as an on-chip oscillator, as shown in Figure 21-1.
C3 SXOUT
C2
4.19MHz
XIN VSS
C4 32.768KHz
SXIN VSS
Recommend Crystal Oscillator Ceramic Resonator C1,C2 = 20pF C1,C2 = 20pF
Recommend C3,C4 = 30pF
Crystal or Ceramic Oscillator
Open
XOUT REXT
XOUT Select R value according to AC Characteristics. The Cap. is built in(5pF).
External Clock
XIN
XIN
External Oscillator
RC Oscillator Figure 21-1 Oscillation Circuit
Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. In addition, see Figure 21-2 for the layout of the crystal.
XOUT
Note: Minimize the wiring length. Do not allow the wiring to intersect with other signal conductors. Do not allow the wiring to come near changing high current. Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground it to any ground pattern where high current is present. Do not fetch signals from the oscillator.
XIN
Figure 21-2 Layout of Oscillator PCB circuit
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22. RESET
The GMS81C5108 have two types of reset generation procedures; one is an external reset input, the other is a watchOn-chip Hardware Program counter RAM page register G-flag Operation mode (PC) (RPR) (G) Initial Value (FFFFH) - (FFFEH) 0 0 Main-frequency clock
dog timer reset. Table 22-1 shows on-chip hardware initialization by reset action.
On-chip Hardware Peripheral clock SVD Control registers Voltage Booster Initial Value On Enable Refer to Table 8-1 on page 25 Disable
Table 22-1 Initializing Internal Status by Reset Action
22.1 External Reset Input
The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin to low for at least 8 oscillator periods, within the operating voltage range and oscillation stable, it is applied, and the internal state is initialized. After reset, 65.5ms (at 4MHz) add with 7 oscillator periods are required to start execution as shown in Figure 22-2. Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before read or tested it. When the RESET pin input goes to high, the reset operation is released and the program execution starts at the vector address stored at FFFEH - FFFFH. A connection for simple power-on-reset is shown in Figure 22-1.
VDD VDD 100k RESET + - GND 1uF MCU Mask Option
Figure 22-1 Simple Power-on-Reset Circuit
1
2
3
4
5
6
7
~ ~
System Clock
~ ~
RESET
~ ~
ADDRESS BUS DATA BUS
?
?
?
?
FFFE FFFF Start
~~ ~~
?
?
?
?
FE
ADL
ADH
OP
Stabilization Time tST = 65.5mS at 4MHz
Figure 22-2 Timing Diagram after RESET
~ ~
RESET Process Step 1 fMAIN /1024 MAIN PROGRAM tST = x 256
22.2 Watchdog Timer Reset
Refer to "13.2 Watch Dog Timer" on page 57.
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23. SUPPLY VOLTAGE DETECTION
The GMS81C5108 has an on-chip low voltage detection circuitry to detect the VDD voltage. A configuration register, SCMR, can enable or disable the low voltage detect circuitry. This GMS81C5108 has two level detector(SVD0, SVD1). The SVD0 flag is set when the V DD falls below 2.2V and if the V DD is rise above 2.2V the SVD0 is cleared automatically. The SVD1 flag is set when the VDD falls below 1.7V and if this flag is set once, it is
SCMR (System Clock Mode Register)
MSB R/W R/W R/W R R/W R/W R/W
not cleared automatically although the VDD rises above 1.7V. It can be cleared by writing. If the SVD1 is set, the MCU can be RESET or frozen by the flag SVRT. In the in-circuit emulator, supply voltage detection is not implemented and user can not experiment with it. Therefore, after final development of user program, this function may be experimented or evaluated.
LSB R/W
ADDRESS: 0F5H INITIAL VALUE: 00H SYCC[1:0] (System clock control) 00: main clock on 01: main clock on 10: sub clock on (main clock on) 11: sub clock on (main clock off)
SCS[1:0] (System clock source select) fMAIN/2 or fSUB/2 fMAIN/23 or fSUB/23 fMAIN/24 or fSUB/24 6 6 SVRT (System Reset Control by SVD1 Bit) fMAIN/2 or fSUB/2 0 : System reset by SVD1 Flag 1 : Don't system reset by SVD1 Flag (Freeze) SVD[1:0] (SVD Flag) SVD0 : set at VDD=2.2V SVD1 : set at VDD=1.7V SVEN (SVD Operation Enable Bit) 0 : SVD Operation Enable 1 : SVD Operation Disable
* The values of 1.7V and 2.2V could be changed by 0.2V according to the process of work.
Figure 23-1 Low Voltage Detector Register
VDD 65.5mS
SVD MAX SVD MIN
Internal RESET VDD When SVRT = 0 Internal RESET VDD
SVD MAX SVD MIN 65.5mS t < 65.5mS SVD MAX SVD MIN 65.5mS
Internal RESET VDD
SVD MAX SVD MIN
System Clock When SVRT = 1 VDD SVD MAX SVD MIN
System Clock
Figure 23-2 Power Fail Processor Situations
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24. DEVEMOPMENT TOOLS
24.1 OTP Programming
The GMS87C5108 is an OTP (One Time Programmable) microcontrollers. Its internal user memory is constructed with EPROM (Electrically Programmable Read Only Memory). The OTP microcontroller is generally used for chip evaluation, first production, small amount production, fast mass production, etc. Blank OTP's internal EPROM is filled by 00H, not FFH.
Programming Procedure 1. Select device GMS87C5108 you want. 2. Load the *.OTP file from the PC. The file is composed of Motorola-S1 format. 3. Set the programming address range as below table.
Address Buffer start address Buffer end address Device start address Set Value E000H FFFFH E000H
Note: In any case, you have to use the *.OTP file for programming, not the *.HEX file. After assemble, both OTP and HEX file are generated by automatically. The HEX file is used during program emulation on the emulator.
How to Program
To program the OTP devices, user can use Hynix own programmer. Hynix own programmer list Manufacturer: Hynix Semiconductor Programmer: Choice-Sigma Choice-Gang4 The Choice-Sigma is a Hynix Universal Single Programmer for all of Hynix OTP devices, also the Choice-Gang4 can program four OTPs at once for Hynix OTP. Ask to Hynix sales part for purchasing or more detail
4. Mount the socket adapter on the programmer. 5. Start program/verify. Pin Function
VPP (Program Voltage) VPP is the input for the program voltage for programming the EPROM. CE (Chip Enable) CE is the input for programming and verifying internal EPROM. OE (Output Enable) OE is the input of data output control signal for verify. A0~A15 (Address Bus) A0~A15 are address input pins for internal EPROM. O0~O7 (EPROM Data Bus) These are data bus for internal EPROM.
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J_USERB
CONNECTA CONNECTB
J_USERA
GND VCL1 VLCDC CB GND REMOUT (TONED) GND R36 R34 R21 R23 R25 R27 R16 R14 R12 R10 R06 R04 R02 R00 R32 R30 +5V
POWER
RUN
STOP
SLEEP
SW 1
SW 2
RESET
X2
21
/RESET XOUT OFF ON J_USERB J_USERA
24.2 Emulator S/W Setting
External Oscillator Socket +5V
X1 (OSC) CONNECTC
V_USER
SEG46 SEG44 SEG42 SEG40 SEG38 VREG COM1/S36 COM3/S34 SEG32 SEG30 SEG28 SEG26 SEG24 SEG22 SEG20 SEG18 SEG16 SEG14 SEG12 SEG10 SEG8 SEG6 SEG4 SEG2 SEG0
GND SEG47 VCL0 SEG45 VCL2 SEG43 CA SEG41 GND SEG39 /U_RST SEG37 U_XOUT COM0 GND COM2/S35 R37 SEG33 R35 SEG31 R20 SEG29 R22 SEG27 R24 SEG25 R26 SEG23 R17 SEG21 R15 SEG19 R13 SEG17 R11 SEG15 R07 SEG13 R05 SEG11 R03 SEG9 R01 SEG7 R33 SEG5 R31 SEG3 +5V SEG1
1 2 3 4 5 6 7
1 2
SW 4
CHOICE-Dr. EVA 81C51 B/D Rev 1.0 S/N. ---------------
LCD_VDD
VR1
VR2
VLCDC
SW 5
GMS81C5108
GMS81C51 EVA
OFF ON
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DIP Switch and VR Setting
Before execute the user program, keep in your mind the below configuration DIP S/W, VR SW1 Description Emulator Reset Switch. Reset the Emulator. ON/OFF Setting Reset the Emulator. Normally OFF. EVA. chip can be reset by external user target system board. ON : Reset is available by user target system board. OFF : MCU is reset by REST switch on EVA. board. Normally OFF. MCU XOUT pin are disconnected by Emulator internally. Some circumstance user may connect this circuit. ON : Output XOUT signal OFF : Disconnect circuit
SW2-1
1
OFF ON
EVA. Chip
RESET pin
SW2
SW2-2
2
EVA. Chip Oscillator
XOUT pin
External Resistor and Capacitor VDD Adjust Contrast SW4-1 VR1 50k
1 2 3
OFF ON
VCL2
SW4-2
VCL1
10k x 3 SW4-3
Normally ON. It serves the external bias resistors. If user want to use external circuit instead of internal R, turn on these switches.
VCL0
0.47uF x 3
VSS
SW4
4 5 6
LCD Voltage booster circuit.
Must be ON position. It is used for the GMS81C5108. Must be OFF position. This switch decide the Stack page 0 (off) or page 1 (on). ON : For the GMS81C7XXX OFF : For the GMS81C5108
VDD
7
Select the Stack Page.
EVA. Chip
LVD pin
SW4-8
8 GMS81C5108 detect the VDD voltage but Emulator can not do because Emulator can not operate if VDD is below normal opr. voltage (5V), This switch serves LVD environment through the applying 0V to LVD pin of EVA. chip during 5V normal operation.
Position ON during normal operation. ON : Normal operation OFF : Force to detect the LVD, refer to "23. SUPPLY VOLTAGE DETECTION" on page 82.
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DIP S/W, VR SW5 1 2
OFF ON
Description Internal power supply to sub-oscillation circuit. Reserved for other purpose. Adjust the LCD contrast. It control the VCL2 voltage. Refer to above SW4-1,2,3 figure. Reserved for other purpose.
ON/OFF Setting Must be ON position. Must be OFF position. Adjust the proper position as well as LCD display good. Don't care.
VR1 VR2
-
86
JUNE 2001 Ver 1.0
GMS81C5108
Book History
This Book Ver 1.0 (JUNE 2001) First edition.
JUNE 2001 Ver 1.0
87
APPENDIX
GMS81C5108 APPENDIX
A. CONTROL REGISTER LIST
Address 00C0 00C1 00C2 00C3 00C8 00C9 00CA 00CB 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 00D8 00D9 00DA 00DB 00DC 00DD 00DE 00E0 Register Name R0 port data register R1 port data register R2 port data register R3 port data register R0 port I/O direction register R1 port I/O direction register R2 port I/O direction register R3 port I/O direction register R0 port pull-up register R1 port pull-up register R2 port pull-up register R3 port pull-up register R0 port open drain control register R1 port open drain control register R2 port open drain control register R3 port open drain control register Ext. interrupt edge selection register Port selection register Interrupt enable low register Interrupt enable high register Interrupt request flag low register Interrupt request flag high register Sleep mode register Timer 0 mode register Timer 0 counter register 00E1 Timer 0 data register Timer 0 input capture register 00E2 00E3 Timer 1 mode register Timer 1 data register PWM0 pulse period register Timer 1 counter register 00E4 Timer 1 input capture register PWM0 pulse duty register 00E5 00EC 00ED PWM0 high register A/D converter mode register A/D converter data register Symbol R0 R1 R2 R3 R0DR R1DR R2DR R3DR R0PU R1PU R2PU R3PU R0CR R1CR R2CR R3CR IESR PMR IENL IENH IRQL IRQH SMR TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWMHR ADMR ADDR R/W R/W R/W R/W R/W W W W W W W W W W W W W R/W R/W R/W R/W R/W R/W R/W R/W R W R R/W W W R R R/W W R/W R Initial Value
76543210
Page 32 32 33 33 32 32 33 33 32 32 33 33 32 32 33 33 69 32 65 65 65 65 39 45 45 45 45 45 45 45 45 45 45 45 58 58
00000000 00000000 - - - - 0000 - - - - 0000 00000000 00000000 - - - - 0000 - - - - 0000 00000000 00000000 - - - - 0000 - - - - 0000 00000000 00000000 - - - - 0000 - - - - 0000 - - 000000 - 0 - 00000 - 0000 - - - 0000000 - 0000 - - - 0000000 -------0 - - 000000 00000000 11111111 00000000 00000000 11111111 11111111 00000000 00000000 00000000 - - - - 0000 - 0 - - 0001 xxxxxxxx
JUNE 2001 Ver 1.0
i
GMS81C5108 APPENDIX
Address 00EF 00F0 00F1 00F3 00F4 00F5 00F6 00F7 00F8 00F9 00FA 00FB 00FC 00FD 00FE 00FF
Register Name Watch timer mode register Key scan mode register LCD control register RAM paging register Basic interval timer register Clock control register System clock mode register Remocon mode register Carrier frequency high selection Carrier frequency low selection Remocon data high register Remocon data low register Remocon data counter Remocon output data register Remocon output buffer Buzzer data register Serial I/O mode register Serial I/O data register
Symbol WTMR KSMR LCR RPR BITR CKCTLR SCMR RMR CFHS CFLS RDHR RDLR RDC RODR ROB BDR SIOM SIOD
R/W R/W R/W R/W R/W R W R/W R/W W W W W R R/W R/W W R/W R/W
Initial Value
76543210
Page 56 70 72 73 43 43 34 76 76 76 76 76 76 76 76 60 62 62
- 0000000 00000000 00000000 - - - - - - 00 00000000 - - - - 0111 00000000 - 0000000 - - 111111 - - 111111 11111111 11111111 00000000 -------0 -------0 00000000 00000001 xxxxxxxx
ii
JUNE 2001 Ver 1.0
GMS81C5108 APPENDIX
B. INSTRUCTION
B.1 Terminology List
Terminology A X Y PSW #imm dp !abs [] {} { }+ .bit A.bit dp.bit M.bit rel upage n + x Accumulator X - register Y - register Program Status Word 8-bit Immediate data Direct Page Offset Address Absolute Address Indirect expression Register Indirect expression Register Indirect expression, after that, Register auto-increment Bit Position Bit Position of Accumulator Bit Position of Direct Page Memory Bit Position of Memory Data (000H~0FFFH) Relative Addressing Data U-page (0FF00H~0FFFFH) Offset Address Table CALL Number (0~15) Addition
0 Bit Position
Description
Upper Nibble Expression in Opcode
y - x / ()
1 Bit Position
Upper Nibble Expression in Opcode
Subtraction Multiplication Division Contents Expression AND OR Exclusive OR NOT Assignment / Transfer / Shift Left Shift Right Exchange Equal Not Equal
~ =
JUNE 2001 Ver 1.0
iii
GMS81C5108 APPENDIX
B.2 Instruction Map
LOW 00000 HIGH
00 -
00001 01 SET1 dp.bit
00010 02
00011 03
00100 04 ADC #imm SBC #imm CMP #imm OR #imm AND #imm EOR #imm LDA #imm LDM dp,#imm
00101 05 ADC dp SBC dp CMP dp OR dp AND dp EOR dp LDA dp STA dp
00110 06 ADC dp+X SBC dp+X CMP dp+X OR dp+X AND dp+X EOR dp+X LDA dp+X STA dp+X
00111 07 ADC !abs SBC !abs CMP !abs OR !abs AND !abs EOR !abs LDA !abs STA !abs
01000 08 ASL A ROL A LSR A ROR A INC A DEC A TXA
01001 09 ASL dp ROL dp LSR dp ROR dp INC dp DEC dp LDY dp STY dp
01010 0A TCALL 0
01011 0B SETA1 .bit
01100 0C BIT dp COM dp TST dp CMPX dp CMPY dp DBNE dp LDX dp STX dp
01101 0D POP A POP X POP Y POP PSW CBNE dp+X XMA dp+X LDX dp+Y STX dp+Y
01110 0E PUSH A PUSH X PUSH Y PUSH PSW TXSP
01111 0F BRK BRA rel PCALL Upage RET INC X DEC X DAS
000
BBS BBS A.bit,rel dp.bit,rel
001
CLRC
TCALL CLRA1 2 .bit TCALL 4 TCALL 6 NOT1 M.bit OR1 OR1B
010
CLRG
011
DI
100
CLRV
TCALL AND1 8 AND1B TCALL EOR1 10 EOR1B TCALL 12 TCALL 14 LDC LDCB STC M.bit
101
SETC
TSPX
110
SETG
XCN
111
EI
TAX
XAX
STOP
LOW 10000 HIGH
10 BPL rel BVC rel BCC rel BNE rel BMI rel BVS rel BCS rel BEQ rel
10001 11 CLR1
dp.bit
10010 12 BBC
A.bit,rel
10011 13 BBC
dp.bit,rel
10100 14 ADC {X} SBC {X} CMP {X} OR {X} AND {X} EOR {X} LDA {X} STA {X}
10101 15 ADC !abs+Y SBC !abs+Y CMP !abs+Y OR !abs+Y AND !abs+Y EOR !abs+Y LDA !abs+Y STA !abs+Y
10110 16 ADC [dp+X] SBC [dp+X] CMP [dp+X] OR [dp+X] AND [dp+X] EOR [dp+X] LDA [dp+X] STA [dp+X]
10111 17 ADC [dp]+Y SBC [dp]+Y CMP [dp]+Y OR [dp]+Y AND [dp]+Y EOR [dp]+Y LDA [dp]+Y STA [dp]+Y
11000 18 ASL !abs ROL !abs LSR !abs ROR !abs INC !abs DEC !abs LDY !abs STY !abs
11001 19 ASL dp+X ROL dp+X LSR dp+X ROR dp+X INC dp+X DEC dp+X LDY dp+X STY dp+X
11010 1A TCALL 1 TCALL 3 TCALL 5 TCALL 7 TCALL 9 TCALL 11 TCALL 13 TCALL 15
11011 1B JMP !abs CALL !abs MUL
11100 1C BIT !abs TEST !abs
11101 1D ADDW dp SUBW dp
11110 1E LDX #imm LDY #imm CMPX #imm CMPY #imm INC Y DEC Y
11111 1F JMP [!abs] JMP [dp] CALL [dp] RETI
000
001
010
TCLR1 CMPW !abs dp CMPX !abs CMPY !abs XMA dp LDX !abs STX !abs LDYA dp INCW dp DECW dp STYA dp CBNE dp
011
DBNE Y
100
DIV XMA {X} LDA {X}+ STA {X}+
TAY
101
TYA
110
XAY
DAA
111
XYX
NOP
iv
JUNE 2001 Ver 1.0
GMS81C5108 APPENDIX
B.3 Instruction Set
Arithmetic / Logic Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
Mnemonic
ADC #imm ADC dp ADC dp + X ADC !abs ADC !abs + Y ADC [ dp + X ] ADC [ dp ] + Y ADC { X } AND #imm AND dp AND dp + X AND !abs AND !abs + Y AND [ dp + X ] AND [ dp ] + Y AND { X } ASL A ASL dp ASL dp + X ASL !abs CMP #imm CMP dp CMP dp + X CMP !abs CMP !abs + Y CMP [ dp + X ] CMP [ dp ] + Y CMP { X } CMPX #imm CMPX dp CMPX !abs CMPY #imm CMPY dp CMPY !abs COM dp DAA DAS DEC A DEC dp DEC dp + X DEC !abs DEC X DEC Y
Op Code
04 05 06 07 15 16 17 14 84 85 86 87 95 96 97 94 08 09 19 18 44 45 46 47 55 56 57 54 5E 6C 7C 7E 8C 9C 2C DF CF A8 A9 B9 B8 AF BE
Byte No
2 2 2 3 3 2 2 1 2 2 2 3 3 2 2 1 1 2 2 3 2 2 2 3 3 2 2 1 2 2 3 2 2 3 2 1 1 1 2 2 3 1 1
Cycle No
2 3 4 4 5 6 6 3 2 3 4 4 5 6 6 3 2 4 5 5 2 3 4 4 5 6 6 3 2 3 4 2 3 4 4 3 3 2 4 5 5 2 2 Arithmetic shift left
C
Operation
Add with carry. A(A)+(M)+C
Flag
NVGBHIZC
NV--H-ZC
Logical AND A (A)(M) N-----Z-
76543210
N-----ZC
"0"
Compare accumulator contents with memory contents (A) -(M)
N-----ZC
Compare X contents with memory contents (X)-(M) Compare Y contents with memory contents (Y)-(M) 1'S Complement : ( dp ) ~( dp ) Decimal adjust for addition Decimal adjust for subtraction Decrement M (M)-1 N-----ZC N-----ZN-----ZC N-----ZC N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZN-----ZC
JUNE 2001 Ver 1.0
v
GMS81C5108 APPENDIX
No.
44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 DIV
Mnemonic
Op Code
9B A4 A5 A6 A7 B5 B6 B7 B4 88 89 99 98 8F 9E 48 49 59 58 5B 64 65 66 67 75 76 77 74 28 29 39 38 68 69 79 78 24 25 26 27 35 36 37 34 4C CE
Byte No
1 2 2 2 3 3 2 2 1 1 2 2 3 1 1 1 2 2 3 1 2 2 2 3 3 2 2 1 1 2 2 3 1 2 2 3 2 2 2 3 3 2 2 1 2 1
Cycle No
12 2 3 4 4 5 6 6 3 2 4 5 5 2 2 2 4 5 5 9 2 3 4 4 5 6 6 3 2 4 5 5 2 4 5 5 2 3 4 4 5 6 6 3 3 5 Subtract with Carry Logical shift right Increment M (M)+1 Exclusive OR A (A)(M)
Operation
Divide : YA / X Q: A, R: Y
Flag
NVGBHIZC NV--H-Z-
EOR #imm EOR dp EOR dp + X EOR !abs EOR !abs + Y EOR [ dp + X ] EOR [ dp ] + Y EOR { X } INC A INC dp INC dp + X INC !abs INC X INC Y LSR A LSR dp LSR dp + X LSR !abs MUL OR #imm OR dp OR dp + X OR !abs OR !abs + Y OR [ dp + X ] OR [ dp ] + Y OR { X } ROL A ROL dp ROL dp + X ROL !abs ROR A ROR dp ROR dp + X ROR !abs SBC #imm SBC dp SBC dp + X SBC !abs SBC !abs + Y SBC [ dp + X ] SBC [ dp ] + Y SBC { X } TST dp XCN
N-----Z-
N-----ZC N-----ZN-----ZN-----ZN-----ZN-----ZN-----ZC
76543210 C "0"
Multiply : YA Y x A Logical OR A (A)(M)
N-----Z-
N-----Z-
Rotate left through Carry
C 76543210
N-----ZC
Rotate right through Carry
76543210 C
N-----ZC
A ( A ) - ( M ) - ~( C ) NV--HZC
Test memory contents for negative or zero, ( dp ) - 00H Exchange nibbles within the accumulator A7~A4 A3~A0
N-----ZN-----Z-
vi
JUNE 2001 Ver 1.0
GMS81C5108 APPENDIX
Register / Memory Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
Mnemonic
LDA #imm LDA dp LDA dp + X LDA !abs LDA !abs + Y LDA [ dp + X ] LDA [ dp ] + Y LDA { X } LDA { X }+ LDM dp,#imm LDX #imm LDX dp LDX dp + Y LDX !abs LDY #imm LDY dp LDY dp + X LDY !abs STA dp STA dp + X STA !abs STA !abs + Y STA [ dp + X ] STA [ dp ] + Y STA { X } STA { X }+ STX dp STX dp + Y STX !abs STY dp STY dp + X STY !abs TAX TAY TSPX TXA TXSP TYA XAX XAY XMA dp XMA dp+X XMA {X} XYX
Op Code
C4 C5 C6 C7 D5 D6 D7 D4 DB E4 1E CC CD DC 3E C9 D9 D8 E5 E6 E7 F5 F6 F7 F4 FB EC ED FC E9 F9 F8 E8 9F AE C8 8E BF EE DE BC AD BB FE
Byte No
2 2 2 3 3 2 2 1 1 3 2 2 2 3 2 2 2 3 2 2 3 3 2 2 1 1 2 2 3 2 2 3 1 1 1 1 1 1 1 1 2 2 1 1
Cycle No
2 3 4 4 5 6 6 3 4 5 2 3 4 4 2 3 4 4 4 5 5 6 7 7 4 4 4 5 5 4 5 5 2 2 2 2 2 2 4 4 5 6 5 4 Load Y-register Y(M) Load accumulator A(M)
Operation
Flag
NVGBHIZC
N-----Z-
X- register auto-increment : A ( M ) , X X + 1 Load memory with immediate data : ( M ) imm Load X-register X (M) N-----Z--------
N-----Z-
Store accumulator contents in memory (M)A --------
X- register auto-increment : ( M ) A, X X + 1 Store X-register contents in memory (M) X Store Y-register contents in memory (M) Y Transfer accumulator contents to X-register : X A Transfer accumulator contents to Y-register : Y A Transfer stack-pointer contents to X-register : X sp Transfer X-register contents to accumulator: A X Transfer X-register contents to stack-pointer: sp X Transfer Y-register contents to accumulator: A Y Exchange X-register contents with accumulator :X A Exchange Y-register contents with accumulator :Y A Exchange memory contents with accumulator (M)A Exchange X-register contents with Y-register : X Y N-----Z--------------N-----ZN-----ZN-----ZN-----ZN-----ZN-----Z----------------------
JUNE 2001 Ver 1.0
vii
GMS81C5108 APPENDIX
16-BIT operation
No.
1 2 3 4 5 6 7
Mnemonic
ADDW dp CMPW dp DECW dp INCW dp LDYA dp STYA dp SUBW dp
Op Code
1D 5D BD 9D 7D DD 3D
Byte No
2 2 2 2 2 2 2
Cycle No
5 4 6 6 5 5 5
Operation
16-Bits add without Carry YA ( YA ) + ( dp +1 ) ( dp ) Compare YA contents with memory pair contents : (YA) - (dp+1)(dp) Decrement memory pair ( dp+1)( dp) ( dp+1) ( dp) - 1 Increment memory pair ( dp+1) ( dp) ( dp+1) ( dp ) + 1 Load YA YA ( dp +1 ) ( dp ) Store YA ( dp +1 ) ( dp ) YA 16-Bits subtract without carry YA ( YA ) - ( dp +1) ( dp)
Flag
NVGBHIZC NV--H-ZC N-----ZC N-----ZN-----ZN-----Z-------NV--H-ZC
Bit Manipulation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mnemonic
AND1 M.bit AND1B M.bit BIT dp BIT !abs CLR1 dp.bit CLRA1 A.bit CLRC CLRG CLRV EOR1 M.bit EOR1B M.bit LDC M.bit LDCB M.bit NOT1 M.bit OR1 M.bit OR1B M.bit SET1 dp.bit SETA1 A.bit SETC SETG STC M.bit TCLR1 !abs TSET1 !abs
Op Code
8B 8B 0C 1C y1 2B 20 40 80 AB AB CB CB 4B 6B 6B x1 0B A0 C0 EB 5C 3C
Byte No
3 3 2 3 2 2 1 1 1 3 3 3 3 3 3 3 2 2 1 1 3 3 3
Cycle No
4 4 4 5 4 2 2 2 2 5 5 4 4 5 5 5 4 2 2 2 6 6 6
Operation
Bit AND C-flag : C ( C ) ( M .bit ) Bit AND C-flag and NOT : C ( C ) ~( M .bit ) Bit test A with memory : Z ( A ) ( M ) , N ( M7 ) , V ( M6 ) Clear bit : ( M.bit ) "0" Clear A bit : ( A.bit ) "0" Clear C-flag : C "0" Clear G-flag : G "0" Clear V-flag : V "0" Bit exclusive-OR C-flag : C ( C ) ( M .bit ) Bit exclusive-OR C-flag and NOT : C ( C ) ~(M .bit) Load C-flag : C ( M .bit ) Load C-flag with NOT : C ~( M .bit ) Bit complement : ( M .bit ) ~( M .bit ) Bit OR C-flag : C ( C ) ( M .bit ) Bit OR C-flag and NOT : C ( C ) ~( M .bit ) Set bit : ( M.bit ) "1" Set A bit : ( A.bit ) "1" Set C-flag : C "1" Set G-flag : G "1" Store C-flag : ( M .bit ) C Test and clear bits with A : A - ( M ) , ( M ) ( M ) ~( A ) Test and set bits with A : A-(M), (M) (M)(A)
Flag
NVGBHIZC -------C -------C MM----Z-
---------------------0 --0-----0--0---------C -------C -------C -------C --------------C -------C ---------------------1 --1-----------N-----ZN-----Z-
viii
JUNE 2001 Ver 1.0
GMS81C5108 APPENDIX
Branch / Jump Operation
No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mnemonic
BBC A.bit,rel BBC dp.bit,rel BBS A.bit,rel BBS dp.bit,rel BCC rel BCS rel BEQ rel BMI rel BNE rel BPL rel BRA rel BVC rel BVS rel CALL !abs CALL [dp] CBNE dp,rel CBNE dp+X,rel DBNE dp,rel DBNE Y,rel JMP !abs JMP [!abs] JMP [dp] PCALL upage
Op Code
y2 y3 x2 x3 50 D0 F0 90 70 10 2F 30 B0 3B 5F FD 8D AC 7B 1B 1F 3F 4F
Byte No
2 3 2 3 2 2 2 2 2 2 2 2 2 3 2 3 3 3 2 3 3 2 2
Cycle No
4/6 5/7 4/6 5/7 2/4 2/4 2/4 2/4 2/4 2/4 4 2/4 2/4 8 8 5/7 6/8 5/7 4/6 3 5 4 6 Branch if bit clear :
Operation
if ( bit ) = 0 , then pc ( pc ) + rel Branch if bit set : if ( bit ) = 1 , then pc ( pc ) + rel Branch if carry bit clear if ( C ) = 0 , then pc ( pc ) + rel Branch if carry bit set if ( C ) = 1 , then pc ( pc ) + rel Branch if equal if ( Z ) = 1 , then pc ( pc ) + rel Branch if minus if ( N ) = 1 , then pc ( pc ) + rel Branch if not equal if ( Z ) = 0 , then pc ( pc ) + rel Branch if minus if ( N ) = 0 , then pc ( pc ) + rel Branch always pc ( pc ) + rel Branch if overflow bit clear if (V) = 0 , then pc ( pc) + rel Branch if overflow bit set if (V) = 1 , then pc ( pc ) + rel Subroutine call M( sp)( pcH ), spsp - 1, M(sp) (pcL), sp sp - 1, if !abs, pc abs ; if [dp], pcL ( dp ), pcH ( dp+1 ) . Compare and branch if not equal : if ( A ) ( M ) , then pc ( pc ) + rel. Decrement and branch if not equal : if ( M ) 0 , then pc ( pc ) + rel. Unconditional jump pc jump address U-page call M(sp) ( pcH ), sp sp - 1, M(sp) ( pcL ), sp sp - 1, pcL ( upage ), pcH "0FFH" . Table call : (sp) ( pcH ), sp sp - 1, M(sp) ( pcL ),sp sp - 1, pcL (Table vector L), pcH (Table vector H)
Flag
NVGBHIZC ---------------
----------------------------------------------------------------
----------------------
--------
--------
24
TCALL n
nA
1
8
--------
JUNE 2001 Ver 1.0
ix
GMS81C5108 APPENDIX
Control Operation & Etc.
No.
1 2 3 4 5 6 7 8 9 10 11 12 13
Mnemonic
BRK DI EI NOP POP A POP X POP Y POP PSW PUSH A PUSH X PUSH Y PUSH PSW RET
Op Code
0F 60 E0 FF 0D 2D 4D 6D 0E 2E 4E 6E 6F
Byte No
1 1 1 1 1 1 1 1 1 1 1 1 1
Cycle No
8 3 3 2 4 4 4 4 4 4 4 4 5
Operation
Software interrupt : B "1", M(sp) (pcH), sp sp-1, M(s) (pcL), sp sp - 1, M(sp) (PSW), sp sp -1, pcL ( 0FFDEH ) , pcH ( 0FFDFH) . Disable all interrupts : I "0" Enable all interrupt : I "1" No operation sp sp + 1, A M( sp ) sp sp + 1, X M( sp ) sp sp + 1, Y M( sp ) sp sp + 1, PSW M( sp ) M( sp ) A , sp sp - 1 M( sp ) X , sp sp - 1 M( sp ) Y , sp sp - 1 M( sp ) PSW , sp sp - 1 Return from subroutine sp sp +1, pcL M( sp ), sp sp +1, pcH M( sp ) Return from interrupt sp sp +1, PSW M( sp ), sp sp + 1, pcL M( sp ), sp sp + 1, pcH M( sp ) Stop mode ( halt CPU, stop oscillator )
Flag
NVGBHIZC ---1-0------0------1---------------restored --------
--------
14 15
RETI STOP
7F EF
1 1
6 3
restored --------
x
JUNE 2001 Ver 1.0
C. MASK ORDER SHEET
MASK ORDER & VERIFICATION SHEET
GMS81C5108 - UD
Customer should write inside thick line box.
1. Customer Information
Company Name Application Order Date Tel: E-mail address: Name & Signature:
YYYY MM DD
2. Device Information
Package ROM Size OSC Option Reset Pull Up Hitel 80QFP 8K Crystal YES R NO Internet .OTP) )
Fax: Mask Data
Chollian File Name : ( Check Sum : (
0000H
Set "00" in this area
DFFFH E000H FFFFH
.OTP file data
3. Marking Specification (Please check mark into
)
C ustom er's Area
G M S81C 5108-UD YYW W KO R EA G M S81C 5108-U D YYW W KO R EA
If the customer logo & part number must be used in this area, please submit a clean original logo & part number. 4. Delivery Schedule
Date Customer sample Risk order
YYYY MM DD
Quantity pcs pcs
HYNIX Confirmation
YYYY
MM
DD
5. ROM Code Verification
Please confirm out verification data.
YYYY
Verification date: Check sum: Tel: E-mail address: Name & Signature: Fax:
MM
DD
Approval date:
YYYY
MM
DD
I agree with your verification data and confirm you to make mask set. Tel: E-mail address: Name & Signature: Fax:
FEB. 2001 Hynix Sem iconductor Inc.

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